Designing ICs with the 'X' Architecture

This reduction allows designers to target smaller area or higher performance, improved yield and power savings. This is especially applicable in today’s market demands of ever-increasing functionality packaged in smaller, faster and cheaper ICs.

The way to think about the X Architecture is that it is a superset of Manhattan. A typical metal layer configuration is shown in Fig. 1. As shown here, the lower three metal layers continue to be Manhattan to preserve investment in standard cells and IP, while metal 4 and metal 5 tend to be diagonals followed by a vertical metal 6. Thus by interspersing both Manhattan and diagonal layers, the router has 8 degrees of freedom instead of 4 degrees of freedom, resulting in wire length reduction and via reduction benefits.

Though the idea of using diagonal interconnects to reduce wire length may be an obvious one, it turns out that developing an X Architecture implementation system for today’s demanding chips is far from it. One of the most common misconceptions is that X Architecture implementation is only about routing. Of course, routing is involved because of diagonal interconnects, but there is far more to X Architecture implementation.

Existing physical implementation systems cannot simply be retrofitted to support the X Architecture. The underlying infrastructure has to go through substantial innovation to accommodate the diagonals and also to enable the EDA applications that sit on top of the infrastructure.

Innovations in extraction and placement are required as well. The maximum benefits from the X Architecture result when every step in the implementation takes advantage of diagonals.

In some cases, taking advantage of diagonals can be a minor methodology change. For example, when performing RTL synthesis, a designer could use a more aggressive wireload model than they would with Manhattan to account for the fact that wire length will be shorter due to the diagonals.

Fortunately, most of the X Architecture implementation complexities are borne by the implementation system so design engineers can leverage their familiar netlist-to-GDSII flow and still enjoy the benefits afforded by the X Architecture.

This article provides designers an insight into successfully designing with the X Architecture, including a discussion on methodology enhancements in floorplanning and power grid implementations, as well as considerations for placement, routing and optimization.

X Architecture methodology and implementation

Pervasive use of diagonal routing is hallmark of the X Architecture and requires a new, production-proven X Architecture implementation system with innovations in placement, routing, optimization, infrastructure and even graphical display (Figure 2).

Floorplanning

Understanding the strengths of the X Architecture when selecting a design candidate and floorplan will help yield the greatest benefits. The basic floorplanning strategies used by designers today are applicable to X Architecture designs also. There are, however, some new considerations that may not necessarily be applicable for a traditional Manhattan implementation.

The X Architecture gives physical designers the choice of four different directions for the metal layers 4 and above, instead of a choice of just 2 directions in Manhattan. It’s very important for physical designers to make the choice for the preferred routing directions depending on their design profile, particularly the floorplan, in order to achieve balanced routing resources.

To illustrate the point, let’s look at how the layer configuration was chosen on a recent graphics chip. In this 6 signal layer configuration, the first five metal layers were as shown in Fig. 1. The metal 6 was a Manhattan vertical because the last time a vertical resource was used was metal 2.

Similarly, for a 9 metal layer design, metal 7 and 8 would go back to being diagonals with metal 9 as Manhattan horizontal.

The pin assignment for the X Architecture will be substantially different from that of Manhattan. As shown in Figure 3, in a simple abutment floorplan, the pin assignment for a two pin Manhattan connection (shown by ‘M’) would not have been optimal for the X Architecture.

For X implementation purposes, the underlying floorplanning technology has been equipped with the X-aware global router in order to achieve optical pin assignment (shown by ‘X’) for X Architecture. The Cadence X Architecture system includes X-aware First Encounter technology to provide the necessary floorplanning capabilities.

Power grid design

Power grid design and implementation is often a balance between creating a robust distribution network and trying to minimize the impact on design routability. Using Manhattan power stripes in a diagonal signal routing layer as shown in Fig. 4A would be detrimental because it would limit the length of the diagonal signal routes and the diagonal signal routes would have to jump over the Manhattan power stripes every time they run into them.

A general approach when designing an X Architecture power grid is that the stripes on a given layer should align themselves with the preferred routing direction of that layer. This implies that on diagonal layers, diagonal power stripes should be used.

Fig. 4B shows an example of a power grid in a recent graphics chip. Here metal 1 and metal 6 show Manhattan power stripes while metal 4 and metal 5 have diagonal power stripes.

In addition to the selection of the power grid directions, the widths, pitches and via configurations of the power grid should be optimized for the least impact to the signal routing resources. An advantage of using a combination of diagonal and Manhattan power stripes is that it can reduce the distance from a power source to any point in the design resulting in lower IR drop.

It’s not enough to just design diagonal power stripes and diagonal power grids. One has to be able to analyze it for IR drop and electromigration. As an example, the Cadence Design Systems' VoltageStorm solution for power grid analysis, IR drop and electromigration has been extended to handle diagonal power grids.

Placement

The need for enhancements in placement may not be as intuitive as routing. Figure 5A illustrates the need for changes in X Architecture placement.

In a typical Manhattan placer, if you have two cells that need to be placed at a certain distance in order to achieve a certain timing constraint then by keeping one of the cells in the middle of the green diamond, the second cell can be placed anywhere on the boundary of the diamond. The distance between the two cells would be exactly the same, irrespective of where the second cell is on the boundary of the diamond, as shown by the red Manhattan routing. In the case of X Architecture, taking advantage of diagonal and Manhattan routing the second cell can now be placed anywhere on the boundary of the brown octagon shown in Fig. 5A.

Mathematically, the octagon is 41% larger than the diamond for the same routing distance between the cells as shown with blue routing. This additional flexibility in placement can substantially reduce design congestion and provides many more choices to meet the timing constraint. If the design does not have a congestion problem, the cells can be placed in a smaller octagon, as shown in Fig. 5(B), which has the same area as the Manhattan diamond, and in the process achieve shorter wirelength as with the blue wire being shorter than the red.

Routing

As mentioned earlier, the X Architecture should be considered as a superset of Manhattan because the implementation uses both Manhattan and diagonal wires. The ability to route with 8 degrees of freedom can also have very powerful implications when routing around obstructions.

Let’s look at an example of how this combination of Manhattan and diagonal routing can be leveraged. Fig. 6 shows a typical top-level floorplan. The optimal path for the two-pin connection that’s shown on the right side of the floorplan between point A in the bottom right and point B in the top middle would be going vertical between IP blocks, then diagonal followed by vertical, and again horizontal.

By taking advantage of the X Architecture, and by taking advantage of a system that’s enabled to have different preferred directions for different regions, as well as different pitches for different directions on the same layer, one could achieve an optimal path on the same layer without having to change the layers (Figure 6). This is a good illustration of the power of the X Architecture.

Extraction

With X Architecture implementation, new and different metal shapes like the ones shown in Fig. 7 come into play because of interactions between Manhattan and diagonal routes. These shapes have to be recognized, processed and modeled accurately in extraction.

Clearly, extraction technology has to go through substantial innovations and as an example, Cadence extraction technology has been extended to handle diagonal extraction.

Metal fill, via insertion and shielding

There are several additional things that physical designers have to complete when doing Manhattan implementation, and the X Architecture implementation is no different. These include shielding for critical nets such as clock nets; metal fill insertion for CMP purposes (square, diamond or rectangular metal fill to achieve required density); and redundant via insertion for the transitions between diagonal to diagonal, diagonal to Manhattan, and Manhattan to Manhattan as shown below in Fig. 8.

Notice the interesting shapes of the double cut vias. For square cuts, the corners of the cut protrude from the wire. Again, the X implementation system will automatically address the via implementation without the user having to worry about the optimized via shapes and double-cut via strategies.

Figure 8a — Shielding for a diagonal route.

Figure 8b — Square metal fill within diagonal routing.

Familiar flow, sign-off tools and standard formats

While developing the X Architecture implementation system is a daunting task, and the X Architecture layout may look unique, the design methodology itself will appear very familiar to designers. The key benefit the X Architecture offers — the opportunity to improve the quality of results and lower chip cost — can be employed within the context of existing methodologies.

The X Architecture implementation system is additive to the experience and knowledge designers already have. From floorplanning through placement and routing to extraction, a designer’s existing knowledge of physical implementation is leveraged, making it possible to quickly adopt the new paradigm of the X Architecture.

One of the many common areas that physical designers care deeply about is signoff tools. Designers have grown to trust their signoff tools over the years and they do not like changing them. The good news about X Architecture is that designers can continue to use their existing signoff tools, particularly for their design rule check (DRC), layout versus schematic (LVS), static timing analysis (STA), and also for other things such as crosstalk analysis, signal integrity, IR drop and electromigration analysis.

All the industry-standard formats used in the Manhattan implementation are supported by the X Architecture system as well. In fact, starting with version 5.6, the LEF/DEF format supports diagonal constructs, so CAD engineers developing design environments for the X Architecture can process the information in the standard formats as needed.

Target design criteria

The X Architecture is applicable to the digital design portion of a chip, and the larger the percentage of standard cell logic in a chip, the greater benefits that can be derived from the X Architecture. Typically, high volume designs in the consumer, wireless and graphics market segments tend to be substantially digital and have large portions of standard cell logic. Further, one of their key important areas is die size reduction, leading to cost benefits where the X Architecture is applicable.

The criteria in choosing a design for the X Architecture are the following: either an ASSP or ASIC design, with more than 4 signal routing layers above library cells, near-square aspect ratio and at least 50% random logic area. The closer a design is to these specific criteria, the higher the benefits that can be derived using the X Architecture.

Conclusion

The X Architecture represents a revolutionary step in optimization of on-chip interconnect. As illustrated, the shorter wirelengths provide a potential path to smaller, faster and cheaper integrated circuits. While the introduction of pervasive diagonal wiring will cause changes in tools and algorithms, the existing methodologies and experiences of design teams can be leveraged.

Additionally, signoff tools for static timing analysis, physical verification and analysis require no modification. Maximizing the benefits of the X Architecture is achieved both through the tools and the designer’s ability to conceptualize and utilize the availability of wiring resources, leading to smaller, faster, lower cost silicon.

For further information on the X Architecture please visit the X Initiative website.

Kalyan Thumaty serves as a Cadence Design Systems Vice President and General Manager, responsible for the X Architecture Division. Thumaty previously served as vice president of worldwide applications engineering and services at Simplex Solutions, prior to its acquisition by Cadence.

Robert Lipsey serves as the Methodology Architect, X Architecture, at Cadence Design Systems, Inc.