Cedric Paillard, Semiconductor Insights
Sep 06, 2005 (8:36 AM)
According to one industry analyst, the worldwide handset RF semiconductor market is expected to grow from $5.3 billion in 2004 to $8.26 billion in 2008. Wi-Fi networks are popping up everywhere, and new standards like 802.11n promise to open new doors for Wi-Fi systems in audio and video streaming applications.
Bluetooth devices are now shipping in the millions, sparked by the adoption of the technology in mobile phones, as well as consumer and automotive applications. Although the technology is still under development, UWB, ZigBee, and WiMAX broadband wireless initiatives promise to change the way we network everything from TVs to A/V equipment, security systems, industrial floors, consumer electronics, and beyond.
Despite strong growth prospects, manufacturers of RF semiconductors are being pulled in several directions to address such market demands as:
- Reduced power consumption
- Increased levels of integration to (1) allow the development of single chip solutions integrating RF and baseband (and possibly MAC) functionality; and (2) support multiple standards within the same IC to comply with smaller form factors associated with wireless products
- Improved performance as more RF solutions are being deployed in the same or contiguous bands to avoid interference and improve the overall end-user experience.
To address these requirements, RF companies are investing heavily in process, technology, architecture, and design mechanisms. Just a few years ago, not many people would have expected that receivers built in CMOS would be able to reach 60 GHz, that wireless LAN (WLAN) ICs would be delivered as single-chip CMOS solutions, or even that Texas Instruments (TI) would be shaking up the cost-sensitive handset market with baseband-plus-RF devices produced in 90-nm CMOS. Although those achievements mark key milestones, they hardly represent the status of the RF industry today, but represent the advanced stage where the RF industry should be by the end of this decade.
Today's full CMOS 60-GHz transceiver is an academic exercise highlighting the importance of direct conversion receivers for relatively short-range wireless communications. To avoid using spiral inductors, these designs will likely choose to create metal horseshoe-shaped microstrip lines to be used for the on-chip inductors (Fig. 1). However, for low frequencies (up to 5 GHz), the high-energy dissipation per bit will be an issue. The advantage of this architecture will be useful at higher frequency ranges, 10 GHz and up. This frequency range is where the unlicensed band could be used to send data at gigabit-per-second rates in what may become the WLAN of the future.
1. The latest RFICs are adding enough logic to be considered SoCs.
With the relatively narrow bandwidth requirements of the IEEE 802.11 specifications, WLAN chips are particularly amenable to CMOS. Two of the heavy hitters in the WLAN space (Atheros, with a single-chip 802.11g solution, and Broadcom with a fully integrated 802.11b chip) have CMOS implementations already in commercial production. Also, two startups have direct-conversion transceivers, currently implemented in CMOS, supporting the 802.11a/b/g standards. Implementing a WLAN transceiver for a handset that benefits from CMOS' low power consumption attributes has also been TI's objective with its latest wireless VoIP chip.
An increasing number of manufacturers are building single-chip CMOS transceivers that support all four GSM bands. In addition, TI has a development team working on a CMOS transceiver for both a global-positioning system (GPS) and the GSM/Edge network. Implementing the same architecture (known as the Digital Radio Processor or DRP), TI has released three different products: GSM/EDGE, WLAN VoIP, and Bluetooth. This architecture, tuned for a specific application, is the first step towards multi-band/multi-mode radios and a clear path toward Software Defined Radios (SDR). With the exception of the Bluetooth version, TI’s new architecture still needs to be combined with an external power amplifier (PA) for the GSM and WLAN VoIP solutions.
According to the FCC, SDR's definition is disarmingly simple: "In an SDR, functions that were formerly carried out solely in hardware, such as the generation of the transmitted signal and the tuning and detection of the received radio signal, are performed by software that controls high-speed signal processors." Similarly, the SDR Forum defines an SDR device as one that functions independently of carrier frequencies and can operate within a range of transmission-protocol environments. Architecturally, these definitions suggest transceivers that perform up/down-conversion between baseband and RF, exclusively in the digital domain, reducing the RF interface to a transmit-channel PA, low-noise amplifier (LNA) for the receive path, and minimal analog filtering.
Digitally processing the transmission signal at carrier frequencies presents numerous difficulties that begin with data-converter requirements. Protocols such as GSM and CDMA use frequencies that can exceed 2 GHz, demanding converters that run at 5 GHz or more. Worse, converters require upward of 13 bits of resolution to preserve the dynamic range that allows subsequent processing to reliably extract the signal content. SiGe (silicon germanium) and/or GaAs (gallium arsenide) processes are potentially suitable but neither cheap nor power-efficient. Although the receiver side is especially challenging, transmitters aren't without their problems, such as maintaining linearity conflicting with maximizing transmitter efficiency via switch-mode techniques.
GSM's simple signals allow PAs to run at about 40% efficiency, but a 3G amplifier's linearity requirements can reduce efficiency to about 3%, requiring 700 W for 20 W of transmitting power. Techniques to improve linearity within nonlinear PAs include predistortion, in which compensation circuitry distorts the incoming signal in the opposite direction of the transmitter's transfer characteristics. Such compensation requires digital techniques to calibrate the amplifier for sufficient accuracy but can improve efficiency by 20% or more.
Including the single-chip CMOS PA with the rest of the transceiver and baseband is the ultimate goal to reduce bill of materials (BOM) and form factor. But this presents significant technical challenges including PA efficiencies (causing heat dissipation issues and increased power consumption in transmit mode with some performance degradation), low breakdown voltage due to the use of small geometries, and parasitic coupling with the rest of the analog and digital (substrate noise coupling) design.
The demands on receiver-chain processing can also be stringent, depending heavily on the modulation format and channel bandwidth. Although GSM shares 200 kHz among eight TDMA (time-division multiple-access) slots, 3G services have channel bandwidths as high as 5 MHz that the protocols share between multiple sessions.
This shift from narrowband to wideband mandates DSP techniques and reduces the need for analog filters by moving filtering, channel selection, and baseband processing into the digital domain. The paucity of carrier-speed data converters compels designers to consider RF front ends for up/down conversion to an IF value that converters can handle.
It's generally accepted that receiving is an order of magnitude more difficult than transmitting. Without the necessity of extracting rapidly changing information from signals buried within a sea of noise, transmitter algorithms are relatively simple. And many receiver techniques similarly apply in the reverse direction, so most discussion centers on receiver architectures and how best to adapt schemes to fit within the SDR context. As a result, there's new focus on the direct-conversion architecture. From the viewpoint of semiconductor design cost and complexity, CMOS-based direct conversion techniques are most suitable.
The main problem is overcoming Zero-IF limitations in terms of transmit distortion and receive reliability. The solution for transmit is pre-distortion with I/Q imbalance corrections. The solution for receive is combined auto/cross-correlation detection with I/Q imbalance correction, dc offset correction, diversity, and equalization.
A true single-chip solution includes not only the analog and RF functions but also the physical layer's digital circuits and the media access controller (MAC). However, to realize low-cost solutions, digital functionality must use the latest process node in deep-submicron CMOS technology, such as 0.13 micron, 90-nm, and even lower in the future.
To provide the required dynamic range and power, RF and analog circuits require higher supply voltages than deep-submicron CMOS technologies can support. With supply voltages in digital processes falling to 1.5 V and below, and threshold voltages around 600 mV, there's little headroom available to conduct significant signal processing in the analog domain. As digital processing moves to the latest process node to reduce cost and increase functional density, analog and RF functions lag behind at earlier process nodes, resulting in lower system integration levels and increased system cost.
One particular designer claimed that when designing highly integrated RF circuits in deep submicron CMOS processes, he was faced with a paradigm shift that the time-domain resolution of a digital-signal edge transition is superior to the voltage resolution of analog signals. TI's DRP architecture exploits this paradigm shift by compensating for the weaknesses of modern digital process nodes with respect to analog and RF functions by exploiting the strengths of the process in terms of transition speed and logic density.
An additional technological barrier to fully integrated CMOS is the quality of the passives built above the CMOS transistors. Engineers are starting to think about using more exotic processes with alternating layers, such as benzo-cyclobutene and electroplated copper that are 5 to 10 microns thick. Although these approaches promise higher filter performance and lower power consumption for wideband CDMA handsets, they have the challenges of added costs and interesting packaging challenges. On the other hand, we can expect CMOS inductors with Q values (a ratio between the stored energy and lost energy in an inductor) to reach 40, which are at least twice as high as those achieved with packaged CMOS-based inductors.
A benefit of the higher Q is the lower power consumption achieved in some specific architectures. Engineering teams working on developing high-Q filter circuits using standard CMOS processes and achieving low manufacturing costs are numerous and usually focus initially on a specific application or technology, such as data rates below 2 Mbits/s. New products using these high-Q filters should make their way into wireless products by the end of the year.
Recent innovations for the cellular market include the development of discrete FBAR filters and resonators that should provide lower insertion loss than surface acoustic-wave (SAW) devices. The FBAR filters and duplexers are currently being adopted into CDMA handsets. However, integrating the FBAR on-chip versus using the discrete front-end SAW and FBAR filters will ultimately be decided by the cost difference to manufacture the handsets.
From a cost perspective, innovative structures (involving complex modeling issues) are becoming available to reduce die size. One good example is the Conexant Satellite Tuner CX24113. This part utilizes six VCO circuits to cover the entire band of interest. The appropriate VCO is selected based on the desired satellite channel. The VCO circuits consist of a center-tapped spiral inductor, a varactor tuning capacitance, a band select switch, a gm stage, and current mirror biasing.
Generally, foundries (and designers) don’t place other circuitry inside the core of the spiral inductor windings due to modeling difficulties. On the CX24113, the varactor and band-select switch are located in the inductor's core. Extensive EM modeling of the VCO structures is required to ensure correct operation.
The gm gain stage of the CX24113 is located between the bias mirrors and the inductor's main body (Fig. 2). The fact that devices are located in the central core of the inductor and the inductors of the separate VCOs are in close proximity indicates that significant modeling efforts were required to ensure correct circuit functionality.
2. The photograph highlights the main components of one of the six VCO structures on a satellite tuner IC. The current mirror bias is located on the left side.
These approaches are used to develop leading-edge commercial RF ICs. Not all of the a approaches are interesting; it will be the approach that proves to be the most cost-effective while achieving the optimum power performance that'll be the one to watch for. Most wireless semiconductor companies have an ongoing in-house program to put all the radios on one die, using an aggressive CMOS process, such as 130 or 90 nm, to preserve cost. And they have an aggressive DSP design program to use generic computational engines to provide both the baseband and MAC functions. These are basically integrated designs of existing in-house silicon IP blocks, with little performance enhancement. Cost-effectively integrating RF into a single-chip device supporting multiple standards at low power is an on-going challenge requiring a clear and well-understood strategic plan.
Today, TI might be the best example with its seven-year development commitment to the company's DRP architecture. Such a strategic plan requires strong financial backing and resources that only a small numbers of RF manufacturers can support. The others will have to (1) define their own strategic plan (business and technical), (2) understand competitive architectures, (3) partner with specialized design houses and/or innovative teams that have solutions to key technology challenges such pre-distortion and filtering and (4) create, acquire and/or license strong IP portfolios around key technology enablers for their market segment.
The wireless semiconductor market is maturing with a concentration of a few large suppliers with their own manufacturing facilities (such as TI), and a series of specialized technical solutions providers with innovative approaches using open capital intensive manufacturing facilities.
About the author
Cedric Paillard is the director of TECHinsights at Semiconductor Insights.