Udhaya Kumar, eInfochips Ltd.(11/14/2005 9:00 AM EST)
Clock network design is a critical task in the design of high performance circuits because both the performance and the functionality of the circuit depend directly on the characteristics of the clock network.
The physical realization of the clock tree network constrains the chip design, and it directly impacts the control of clock skew and jitter. Further, the clock network impacts overall chip power and area because of the large number of buffers and repeaters that are inserted during clock tree synthesis.
There are direct impacts on chip timing as the clock tree drives the overall timing of the chip. Crosstalk from the clock grid affects circuit speed. And the speed and accuracy of the clock net directly contribute to the minimum cycle time of the chip.
The speed of a design is often its costliest component. But clock skew is an important factor in deciding a circuit's cycle time. To achieve optimal clock path delays for high-speed designs, the skew should be reduced — or, alternatively — utilized to the maximum extent possible within the defined cycle time.
In earlier process nodes, choosing clock skew was an optimization trick. But in deep sub-micron (DSM) processes it is a challenge, as it is difficult to control the delay in the clock path due to process variation.
This article discusses strategies for skew management in DSM designs. It covers the role of skew in a design, the types of clock trees used in current technology, the effective use of customized cluster based clock-tree synthesis (CTS), the merits of cluster based CTS for skew controlling and, finally, realistic delay consideration for static timing analysis (STA).
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