English
Using dual port interconnect to resolve multiprocessor system bottlenecks
By Jonathan LaRue and Danny Tseng, Cypress Semiconductor
Jan 18 2006 (12:00 PM), Embedded.com
The use of two or more specialized off-the-shelf processors has provided designers with tremendous computing capabilities and speed. With this growing multiple processor trend, however, comes the need for a high-performance system interconnect to bridge the gap between varying data rates, bus widths and I/O standards.
Additionally, on-board traffic management becomes an issue in many data intensive applications and the last thing designers need is a system interconnect that causes a dataflow bottleneck. The use of high speed dual-ports adds value to any design through its blazing data rates (up to 36 Gb/sec), versatile application in a system, and simple implementation using existing standard memory interfaces.
Jan 18 2006 (12:00 PM), Embedded.com
The use of two or more specialized off-the-shelf processors has provided designers with tremendous computing capabilities and speed. With this growing multiple processor trend, however, comes the need for a high-performance system interconnect to bridge the gap between varying data rates, bus widths and I/O standards.
Additionally, on-board traffic management becomes an issue in many data intensive applications and the last thing designers need is a system interconnect that causes a dataflow bottleneck. The use of high speed dual-ports adds value to any design through its blazing data rates (up to 36 Gb/sec), versatile application in a system, and simple implementation using existing standard memory interfaces.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Dual-port FPGA memory blocks: the ultimate system interconnect solution?
- A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
- Analyzing the Options in High-Bandwidth System Interconnect-or, Serial: It's Not Just for Breakfast
- Using co-design to optimize system interconnect paths
- How designers can survive the embedded multiprocessor revolution
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers