Optimizing DSP functions in advanced FPGA architectures
pldesignline.com
Although FFT and FIR filters may seem complex, in reality they use simple add/subtract/multiply operations. So how can these arithmetic modules, along with shift and pipeline registers in modern FPGAs, be configured in different modes to provide greater flexibility and control with desirable levels of performance? In this "How To" paper, we outline practical steps, along with common mistakes to avoid, for successfully extracting optimal results in your DSP-based FPGA designs.
In high-performance, FPGA-based DSP designs, which typically demand high bandwidth, high throughput, and low operating power, there is very little room for error during the design-planning process. In order to be successful when tackling such designs, you need to understand certain nuances about design specifications and target technology architectures, as well as synthesis tools. With the realization that it is difficult to be an absolute expert on every possible aspect of DSP-based design using programmable logic devices, this article outlines some actions you can take to meet your ultimate objectives when handling these designs.
E-mail This Article | Printer-Friendly Page |
Related Articles
- The case for integrating FPGA fabrics with CPU architectures
- Using FPGAs in Mobile Heterogeneous Computing Architectures
- Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
- Transitioning to Advanced Verification Techniques for FPGAs - Catch-22?
- Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs
New Articles
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study
- I2C Interface Timing Specifications and Constraints