Chris Allsup, Synopsys
(02/20/2006 9:00 AM EST)
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
In an effort to contain costs at the tester, designers have begun to embrace a young, relatively obscure design for test (DFT) methodology known as scan compression that utilizes on-chip circuitry to compress the scan ATPG pattern set without otherwise compromising its fault coverage. Scan compression technology seems to have emerged at just the right time, offering designers the promise of reducing tester costs with only negligible impact on design performance, silicon overhead and engineering resources needed to implement compression on-chip.
(02/20/2006 9:00 AM EST)
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
In an effort to contain costs at the tester, designers have begun to embrace a young, relatively obscure design for test (DFT) methodology known as scan compression that utilizes on-chip circuitry to compress the scan ATPG pattern set without otherwise compromising its fault coverage. Scan compression technology seems to have emerged at just the right time, offering designers the promise of reducing tester costs with only negligible impact on design performance, silicon overhead and engineering resources needed to implement compression on-chip.