By Naseem Aslam, Altera Corp. The combination of a low-cost FPGA and an external physical interface (PHY) chip is uniquely positioned to displace costly, high-risk solutions such as ASICs.
PCI Express is rapidly establishing itself as the successor to PCI. This relatively new bus standard provides higher performance, increased flexibility, and scalability for next-generation systems, as well as maintaining software compatibility with existing PCI applications. As PCI Express becomes the standard interconnect for leading-edge embedded applications, system designers must address the challenges associated with the usability of this new protocol. Today's FPGAs offer an easy-to-use PCI Express solution for the low-cost market segment.
With much higher densities, embedded intellectual property (IP) and higher I/O interconnects, FPGAs have evolved from being used only as glue logic into components that provide integral functionality in digital systems implementations. With the availability of high gate count, features, and support for various third-party EDA tools, designers can use a design flow similar to those used for ASIC devices to create systems employing FPGAs.
To facilitate implementing the PCI Express layers in low-cost and high-volume applications, low-cost FPGAs are available today with an external x1 PCI Express physical interface (PHY). These components are uniquely positioned to displace costly, high-risk solutions such as ASICs, and offer a cost-effective, more flexible and risk-free alternative (Fig 1).
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