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How hybrid Structured ASICs provide low cost solutions for mid-range applications
By Bob Kirk, AMI Semiconductor (AMIS)
Hybrid structured ASICs take the structured idea one step further, because the upper metal layers don't require the same level of precision as the base layers.
ASIC manufacturers that cater to low-to-medium volume applications with medium-logic density requirements have developed a class of custom logic device called a structured ASIC. Targeted at mid-range ASIC applications that require better logic density, lower part price, and reduced power consumption than an FPGA can provide but without the high-volume requirements of a standard-cell ASIC, structured ASICs offer advanced CMOS technologies at low to moderate volumes combined with affordable design-cycle costs and low part prices.
Many electronics applications have wrestled with the divergent demands of low-volume production and low costs. For those applications requiring custom IC designs, the problem gets worse. Many military, industrial, medical, and automotive applications simply can't consume the quantity of silicon required by ASIC manufacturers to achieve the compelling cost savings of a high-volume consumer or computing application. However, the pressure to cut costs is not removed simply because the silicon consumption is low.
Most ASICs are driven by a combination of low cost pressure and unique market-specific requirements. Medium logic density, low-power consumption, or small-footprint applications often have no choice but to use advanced standard-cell ASIC technology to minimize power consumption or meet the cost target.
Hybrid structured ASICs take the structured idea one step further, because the upper metal layers don't require the same level of precision as the base layers.
ASIC manufacturers that cater to low-to-medium volume applications with medium-logic density requirements have developed a class of custom logic device called a structured ASIC. Targeted at mid-range ASIC applications that require better logic density, lower part price, and reduced power consumption than an FPGA can provide but without the high-volume requirements of a standard-cell ASIC, structured ASICs offer advanced CMOS technologies at low to moderate volumes combined with affordable design-cycle costs and low part prices.
Many electronics applications have wrestled with the divergent demands of low-volume production and low costs. For those applications requiring custom IC designs, the problem gets worse. Many military, industrial, medical, and automotive applications simply can't consume the quantity of silicon required by ASIC manufacturers to achieve the compelling cost savings of a high-volume consumer or computing application. However, the pressure to cut costs is not removed simply because the silicon consumption is low.
Most ASICs are driven by a combination of low cost pressure and unique market-specific requirements. Medium logic density, low-power consumption, or small-footprint applications often have no choice but to use advanced standard-cell ASIC technology to minimize power consumption or meet the cost target.
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