Rethinking System-on-chip design at 65 nanometers and below

By Deepak Shankar (dshankar@mirabilisdesign.com), Mirabilis Design
May 17 2006 (9:00 AM), Embedded.com

In recent weeks, executives from major IC houses and EDA companies have been talking about the design challenges facing hardware and software developers as System on Chip designs proceed from 65, to 45, to 32 nanometers.

For example, at the recent Future Electronics Horizons Forum in Budapest, Hungary, both Robert Ober, an executive in AMD’s office of strategy and technology, and Wally Rhines, chairman and CEO of Mentor Graphics, talked about the need to work at higher levels of abstraction to create design files that generate both the hardware and software needed.

Fortunately, they are not alone in the need for such tools and a number of system level design startups companies, with varying degrees of success, have been moving in this direction. And the good news is that we are already, as an industry, more than halfway there, yielding significant improvements in the form of compact architectures, better algorithm implementation, multi-processing speed, power-tradeoffs, memory access and integration of hardware and software design flows.

While getting to the ideal design environments that Ober and Rhines talk about is not easy, it is achievable.

What it takes to get there

But getting to there dealing adequately with the information needed, cross pollination communication and a strong development methodology; depending on the nature of the anticipated system, subsystem, or element of a subsystem.

The structure, composition, scale, or focal point of a new/incremental system design incorporates the talents and gifts of the designer using either a top-down or bottom-up design style. Is a centralized or distributed approach to processing the best approach to achieve the best price/power/performance? Is a symmetrical or asymmetrical topology warranted?

How to answer to such questions? One starts with a conceptual block diagram, refines the design specification based on integrated simulation results, and is made available for everyone in the product hierarchy as early as possible.

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