David Schwan, Micro Linear San Jose, California, USA
Integrating RF IP is not as easy as digital IP. Noise, capacitive coupling and inductance; both self and mutual represent unique challenges to SOC integration.
The Perils of RF IP
The use model for digital IP is a well defined. When digital IP blocks are used, the chief design concerns are circuit timing, signal integrity, IR drop, and electromigration. In general, routing over an IP block is not a problem, and interactions from the inside of an IP block to the inside of another IP block do not occur. Automated flows are readily available to create physical layouts that satisify all electrical parameters.
RF IP blocks however are subject to interactions between blocks due to electromagnetic, capacitive, supply and substrate coupling to the internal wiring inside of the block. These interactions can be significant at distances up to 100 microns for inductance, and thousands of microns for noise. When considering RF IP blocks, there are at least four issues that make them more difficult to integrate in a chip: A) Noise, either into a block or out of a block. Noise can travel thru the substrate or thru the power bussing. B) Parasitic coupling capacitance between an RF block, and the signals routed over it, or next to it. C) Self inductance of any nets connected to the RF block. And lastly, D) mutual inductance between any net within an RF block, to nets in neighboring blocks. Because of these issues, the person doing the integration of RF IP blocks needs to be far more skilled compared to a typical digital Place-and- Route (P&R) engineer. Electrical verification of the placement of RF IP blocks requires different tools than what are used to verify digital designs.
A) Noise is an issue in digital chips, however it is usually limited to signal integrity problems; and example of which is a pair of nets, one an aggressor, and one a victim. Digital signal integrity issues are due to parasitic coupling capacitance between any two nets, and can be fixed automatically by P&R tools. Noise in RF blocks can be noise in the substrate, or noise in the supply lines. A power amplifier (PA) can inject large signals into the substrate. This can cause problems with the operation of the other blocks such as low noise amplifiers (LNA’s) and phase locked loops (PLL’s). Thus devising schemes to make IP blocks insensitive to noise in the substrate is very important.
The placement of blocks can have a large impact on noise supression. It is important to place noise-making blocks far from noise sensitive blocks. Figure A shows a poor floorplan, where the noise making block the PA is adjacent to PLL, and the noisy PLL is placed next to the LNA.
Figure A: Bad Cell Placement
Figure B shows a better floorplan, where the noise making blocks are placed far from the the blocks they will effect. Unfortunately in real SOC design we may not be able to separate blocks in an effective manner.
Figure B: Good Cell Placement
The substrate is typically highly resistive (4- 10Ùcm, or 2KÙ to 10KÙ per square), and by spacing blocks apart by large distances (1,000u to 2,000u) we use the resistance in the substrate to attenuate the noise.
Segregating the power domains is also major consideration. RF chips will typically have many more power and ground domains than a digital chip. Using a single power domain as shown in Figure C, will give poor noise immunity between the PA and the PLL, and between the PLL and LNA.
Figure C: Bad Power Bussing
Separating the power nets between the the blocks eliminates the low impedance paths (metal traces) for noise to travel through, and is shown in Figure D.
Figure D: Noise Isolated Power Bussing
Because the power domains are different, it must be insured that ESD connections between the power nets do not contribute to noise coupling between critical blocks.
Lastly engineering guard rings is of utmost importance. Guard rings can consist of NWell rings, and substrate contacts, and if available can include Deep Trench rings. To be effective for noise isolation, the guard rings should be unbroken, and completely surround the analog or RF block in question. Figure E shows an example of good guard ring design. The substrate is more resistive than the P-Well or N-Well above it. The noise will travel through the lowest impedance path. By putting obstacles in this path, the noise is forced to travel through the higher impedance path where the signal will be attenuated more. Deep trench can be used to provide a deeper obstacle, one which does not conduct, and if properly built can be very effective. Figure F shows a guard ring cross section.
Figure E: Noise Isolated Power Bussing
Figure F: Guard Ring Cross Section
A subset of guard rings is the use of Deep N-Well. Deep N-Well can be used to decrease the amount of NMOS bulk noise entering the substrate. A P-Well inside of Deep N-Well forms two back to back diodes which act as a capacitive divider. Depending on the foundry, Deep N-Well may need to be engineered into the layout from the beginning, or may be added after the cell is designed. Deep N-Well will not keep noise from NPN’s or varactors from entering the substrate, but is usefull for MOS blocks. Figure G shows a Deep N-Well cross section.
Figure G: Deep N-Well Cross Section
B) Digital IP blocks can generally be routed over without problems, routing over an RF blocks, on the other hand, can be deadly. RF and analog blocks have differential circuitry, which can be more sensitive to where and how signals route over the block. Differential circuits can offer better substrate noise immunity, due to the noise being present on both signals, and cancelled out. If a noisy clock line crosses one side of a differential pair, noise will be injected into the signal path. Figure H shows a simple differential amplifier. Figure I shows a balanced layout, and shows a noisy clock line crossing one side of the differential pair.
Figure H: A simple differential amplifier
Figure I: Left Balanced diff amp, Right Balanced diff amp with unbalanced line (red) crossing one side of differential pair.
Parasitic capacitance exists between and nets that cross each other, or run close (1-2 microns away). Ideally the RF block has blockages incorporated in it to disallow routes over the block. The disadvantage of this is that you may have 8 or 9 metal layers available, and the IP block may use 3 to 4 layers All connections to the block should be brought to the edge of the block so that routing does not go over the block and disrupt any critical nets internal to the block. Any routing next to an RF or analog block needs to be carefully looked at. If the IP block has critical nets routed along the edge of the block, any nets routed adjacent to the block can create problems. Ideally the IP block has supply lines around the outside, so that any routing external to the block does not couple into the block.
C) The wires connecting an RF IP block to the pads need to be engineered to account for selfinductance. In the case of a PA 10-12 nets may need to be connected to pads. Having pads in the block means that the IP provider has to engineer the block to account for any self-inductance in the bond pad connections. The circuit area of a PA can be quite small. If the IP block includes the bond pads, the size may be significantly larger than what is necessary. If the block does not have the pad connections, and routing to the pads can have significant self-inductance. Self-inductance is a function of the width, length and thickness. Long wide traces can have pico Henry’s of inductance, which can disrupt the operation of the PA, causing reduced output power, and unwanted spurs. Figure J shows self inductance as a function of wire length and wire width.
Figure J: Self Inductance
Figure K: Power Amplifier with Self Inductance of Bon Pad Connections Included
D) The long wide traces in a PA can also have significant mutual inductance between them. Mutual inductance is represented in circuit simulators using K, which is a measure of inductive coupling between two nets. A value of 1 means high coupling of the two nets. Transformers use numbers close to one. A value of –1 means that the signal is inverted. With processes designed for RF devices, values of K=0.3 can be obtained at distances of 100 microns. This means that IP blocks will interact with each other at large distance (versus the feature size of the devices).
Having an LNA sitting next to a downconverting mixer can cause problems, such as reduced gain. Understanding the internals of the IP block is important. An IP block cannot really be treated as a black box. Unlike digital IP blocks, RF IP blocks may require a full schematic. With proper planning mutual inductance can be minimized. Getting a negative K value between lines can be desirable, and a positive value can represent positive feedback. Figure L shows the mutual inductance interactions of the pad connections. Figure M shows a layout of LNA and Mixer showing the proximity of designed inductors, which can be affected by mutual inductance.
Figure L: Power Amplifier with Self Inductance of Bon Pad Connections Included and arrows showing Mutual Inductors between pads
Figure M – Mixer (left) and LNA (right).
Shielding for mutual inductance can be costly. Dedicating layers above and below a shielded net can consume a large area, and may not work if the frequency of operation means exceeding the skin depth of the shielding. With a typical conductor thickness of 0.7um or thinner in process with transistors of 0.18u or smaller, the shield can be well below the skin depth of the metal well past 10GHz. Any RF energy will pass through the shield metal and couple into the line you wish to shield. In RF processes, one or two thick metal layers are available, and will often be thicker than the skin depth, potentially being useful for shielding, if a thick top metal minus one layer exists. Figure N shows skin depth as a function of frequency. Figure O shows some layout cross sections with the frequency shielding implications.
Figure N: Skin Depth
Figure O: Shields versus Frequency
RF IP blocks interact in ways that digital IP blocks do not. Current place and route tools do not understand the unique issues confronted in integrating RF IP. An RF engineer is required to successfully integrate the blocks into the chip. Schematics are not needed to integrate digital IP, and yet they are likely to be essential for RF IP, in order to understand the effects of parasitic coupling, either capacitive, inductive, and through the substrate. While the IP provider can mitigate some of the integration issues, RF IP blocks will never be as easy to integrate as digital IP blocks.
 “Closed-form formulae for frequency-dependent 3-D interconnect inductance,” Zhaomin Zhu, Xiao Xia, Reinhard Streiter, Gang Ruan, Thomas Otto, Hermann Wolf, and Thomas Gessner, Microelectronic Engineering, Vol. 56 (2001), p. 359-370.
 A skin depth calculator is available at: http://www.microwaves101.com/encyclopedia/calsd epth.cfm