How to use the Trace Port on PowerPC 405 cores

In this tutorial, the author explains how to use the Trace Port on PowerPC 405 cores embedded in FPGAs for software-hardware debug.

By Brad Frieden, Agilent

Editor's note: In this fourth installment of a four-part series on debugging FPGA designs, author Brad Frieden explains how to use the Trace Port on PowerPC 405 processor cores embedded in FPGAs to provide visibility into the program flow.

See also:

Part 1: Using a core-assisted approach to accelerate the debug of FPGA-based DDR II interfaces.

Part 2: How to speed FPGA debug with measurement cores and a mixed-signal oscilloscope

Part 3: Fast insight into MicroBlaze-based FPGA designs with the MicroBlaze Trace Core (MTC).

Common today is the use of one or more embedded processor cores in FPGA-based digital designs. Cost and integration are both reasons to move away from the use of a separate microprocessor chip. This is especially true given new tools that enable easy debug of systems with certain embedded processors. Take, for example, the Xilinx Virtex II Pro and Virtex 4 families of FPGAs, which offer embedded IBM PowerPC 405 processors with a built in "Trace Port." When used in conjunction with an IBM 405 Trace Port inverse assembler on a logic analyzer, this port allows the user to minimize the number of pins required on their FPGA while still providing visibility of program flow on the embedded microprocessor. Without the use of the Trace Port, this would require up to 50 signals to observe. Let's first consider how the Trace Port approach is possible, and we will then discuss the practical steps required in order to realize this kind of debug visibility.

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