Ashutosh Mauskar and Steev Wilcox, Azuro, Inc.
(07/24/2006 9:00 AM EDT), EE Times
Today, power is rapidly replacing performance as the primary concern for many digital chip design teams. Currently, the majority of 90nm design teams perform concurrent analysis and optimization for power, timing and signal integrity at multiple points in their design flow from architecture to routing.
Power, among other things, is a function of operating voltage, switching capacitance, and switching activity (dynamic power = ½CV2f). Standards for capturing operating voltage and switching capacitance are well established in design flows today, but the methodology for capturing the correct switching activities is currently more of an art than a science.
(07/24/2006 9:00 AM EDT), EE Times
Today, power is rapidly replacing performance as the primary concern for many digital chip design teams. Currently, the majority of 90nm design teams perform concurrent analysis and optimization for power, timing and signal integrity at multiple points in their design flow from architecture to routing.
Power, among other things, is a function of operating voltage, switching capacitance, and switching activity (dynamic power = ½CV2f). Standards for capturing operating voltage and switching capacitance are well established in design flows today, but the methodology for capturing the correct switching activities is currently more of an art than a science.