Boris Litinsky, RFMD Navraj Nandra, Synopsys
To decrease costs and increase performance in today’s computing, consumer electronics and communication markets, it is highly advantageous to reduce the development time and the risk of semiconductors and systems-on-chip (SoC’s) devices that make up these products. If a company lacks specific IP needed to differentiate its products, it may choose to purchase or license this IP from a third party. In this article, we will discuss how to select a third party IP vendor, how to verify third party IP, and how to integrate third party IP, with special focus on high speed serial links such as PCI Express.
In order to continually decrease costs and increase performance in today’s highly competitive computing, consumer electronics and communications markets, it is highly advantageous to reduce the development time and the risk of semiconductors and systems-on-chip (SoC’s) devices that make up these products. Some of the factors that adversely impact growth in these markets are related to increasing mask costs especially at the 90 nm nodes and below, longer development and verification cycle times and, especially in consumer electronics, shorter product windows. Third party semiconductor intellectual property (IP) industry has emerged to overcome these issues.
Figure 1: IP is Critical for Productivity
A company that lacks specific IP needed to differentiate its product has a number of options. It may choose to develop this IP internally. However, if it lacks the time, resources, or expertise, it may choose to purchase or license this IP from a third party.
Figure 2: PCI Express and USB Most Common in New Designs
In the aforementioned markets, the trend at the chip interfaces (I/O’s) is to move from parallel data links to multi-gigabit per second (Gb/s) serial binary links. Examples include PCI moving towards PCI express and ATA moving towards SATA. At the same time, the trend is for the serial link to become a peripheral function at the edge of a large ASIC, rather than the core function. For most SoC designers, the value of their IP is in the middle of the chip and the I/O’s should just simply work. Also, board materials for consumer electronic applications are unlikely to change for cost reasons and the impact on performance at speeds greater than 1 Gb/s is significant. In addition, the number of vendors offering serial I/O’s such as PCI Express and SATA are increasing. In this article, we will discuss how to select a third party IP vendor, how to verify third party IP, and how to integrate third party IP, with special focus on high speed serial links such as PCI Express.
Figure 3: DAC Study – Biggest IP Challenge
As can be seen from Figure 3, integration, quality, verification, and cost are the top concerns for the engineers integrating the IP. Consequently, this article will focus on how to evaluate and mitigate risks associated with these issues.
2.0 IP Vendors
Before selecting the IP, one must first select and qualify the vendor who will provide both the intellectual property and hardware/software support. Your chance for first pass silicon success will depend heavily on the quality of the IP and the quality of the support received.
Section 2.1 provides recommendations for selecting an IP vendor. Section 2.2 describes items to consider when doing vendor qualification.
2.1 IP Vendor Selection
When selecting a third party provider, a large number of questions need to be asked:
- How mature is the IP being sold? How many shipping customers?
Third party IP with multiple silicon tape-outs and many shipping customers should be at high maturity level. For IP with no tape-outs or very limited shipping customers, the maturity is lower and the risk is greater.
- Does the IP design team have high-speed design experience?
A team with many years of successful tape-outs will be able to solve your unique layout problems quickly and may be able to customize IP to fit your needs.
- Has this IP taped-out in silicon? What process and foundry?
Look for IP which has undergone multiple tape-outs (especially using the same target foundry and technology) as the one you are targeting for your product. Going to a new vendor or a new process can cause many unforeseen issues.
- Are there any current customers using this IP? If so, can you contact them for reference and to find out if there were any serious problems with the IP?
Customer references can provide valuable insight. Talk to the current and previous customers to find out if there were any issues. Also, find out how quickly these issues were acknowledged and resolved by the vendor.
- How was this IP verified? Has it been certified by any independent standards or compliance body?
IP should be certified by at least one third party vendor. Also, it should be certified compliant by a standards body – if required for this application. See Figure 4 for details on PCI Express compliance requirements.
What are the current errata? Is there a plan to fix the current bugs?
All newly developed intellectual property has bugs. It is important to verify that the vendor acknowledges their mistakes and takes corrective action.
- What is the vendor’s track record in the industry?
Vendors live and breathe by their track record in the industry.
What level of support is the IP vendor willing to provide? On-site? Off-site? Do they have a hotline, world-wide support?
For non-mature (developing technology), it is very important to get the vendor to commit to on-site support. For mature IP, a 24/7 hotline staffed by experts may be highly beneficial.
- How willing is the vendor to customize the IP for my application?
Most intellectual property is highly configurable and customizable to suit your particular needs and performance requirements. However, sometimes you need special features, i.e. such as low-power modes, lower gate count, etc. that are not easily configurable. These features may be the keys to differentiating your product from your competitors. You need to discuss the feasibility and schedule for doing these customization changes up-front with your vendor.
- Can you trust this vendor?
How well has this vendor delivered on their previous promises? Have they ever slipped schedule? How well do they staff up their teams?
- Is the release schedule provided by the vendor reasonable given their current staffing and outside commitments?
Sometimes vendors over commit, so it’s important to confirm whether or not the schedule provided is reasonable.
Figure 4: PCIe Compliance/Interoperability Testing
2.2 IP Vendor Qualification
When doing due diligence on third party IP, it is important to determine the impact of the current bugs (and any other errata) on your intended application. Some bugs may only be present when specific features or configurations are enabled. If the bugs do affect your intended application, it is important to get a written commitment and schedule for their correction.
Although most IP being purchased has been verified to some extent, it may not be sufficient for your application. For mature IP (which has undergone multiple successful tape-outs), this effort could be minimal. However, for new or emerging IP, the certification and verification effort can be quite challenging and lengthy. This effort can be easily underestimated, so good judgment is crucial. For example, a chip using PCI Express I/O may need to be certified at the PCI Express Compliance conference even if the PHY and MAC cores have passed compliance.
The quality of vendor’s support is extremely important when utilizing complex IP. It is imperative to get both verbal and written commitment from the vendor to resolve currently known and future issues that may be found during product development and IP integration.
When using multiple pieces of IP, it may be difficult to pinpoint the exact source of errors. Thus, it’s important to get written commitment from all of your IP vendors to work with each other to resolve whatever issues are found – even if these third party IP vendors are competitors.
3.0 High Speed Serial Links
Although many types of IP exist, the most common and rapidly growing category includes high speed serial I/O cores. These cores are currently deployed in USB, IEEE 1394/Firewire, PCI Express, Serial ATA, and many other products.
In applications where performance, footprint, and cost are paramount, high-speed serial interfaces offer competitive advantages over source-synchronous parallel I/O currently deployed. Consequently, the industry will be moving toward these interfaces to reduce cost and improve performance.
As an engineer or product integrator, you may need to decide whether or not high-speed serial interface are appropriate for your product or application. With this in mind, the following guidelines show the advantages and disadvantages of high speed serial links.
High Speed Serial Link Advantages
- No setup/hold requirements on data lines. Because both data and clock are embedded in the same differential pair, the routing on a printed circuit board is simplified. For parallel I/O, the clock and data pins have to be routed so that all data lanes meet the setup and hold requirements of the source synchronous clock.
- Less pins are required. To achieve the same performance as a single PCI Express link, a comparable parallel interface would need to run at 250 MHz with 8 data and 1 clock pins compared to just 2 pins for the serial link.
- Greater bandwidth per pin. This minimizes the number of pins and associated traces required on the printed circuit board (PCB). Minimizing I/O allows the use of a cheaper chip package with a smaller footprint. Using a cheaper package lowers overall ASIC cost. Moreover, by using a smaller footprint, the printed circuit board costs are minimized because the printed circuit board can have smaller dimensions and use less layers.
- High-speed. A single PCI Express link provides 2.5 Gb/s bandwidth while even the highspeed Pentium 4 Front Side Bus (FSB) runs at a maximum of only 1066 MHz. (Future PCI Express device will support 5 Gb/s bandwidth)
High Speed Serial Link Disadvantages
- Debug is more difficult since a standard logic analyzer cannot easily hook up to a highspeed serial link. Expensive oscilloscopes may be needed to debug signal integrity issues.
- Layout of a serial link is complex due to the need to observe routing and termination requirements for the differential pair.
3.1 Serial Link IP Selection
As with any new technology, the trade-offs between developing the high-speed serial link interface internally and licensing the IP through a third party need to be thoroughly examined.
High speed serial links consists of two layers: the physical layer (PHY) and the media-access layer (MAC). The physical layer is responsible for merging slow incoming data (16 bits at 125 MHz for PCI Express) and clock (125 MHz for PCI Express) and generating two differential high-speed outputs (2.5 Gb/s). The physical layer is also responsible for decoding the incoming high-speed serial data stream. The media access layer handles all high-level functionality, such as flow control, transaction generation, routing, etc. In PCI Express, the MAC layer includes the transaction layer and the data link layer.
Since the physical layer is quite complex (involving high-speed analog design), it will be necessary to license this layer from a third party. Few companies are capable of developing the physical layer internally or in sufficient time.
The MAC can either be developed internally or licensed as well. This will largely depend on the time to market requirements, availability of suitable IP, and verification requirements. For PCI Express, with strict requirements in compatibility, verification, and testing, the development time for the MAC layer can be quite long. For this reason, licensing the MAC as well as the PHY makes sense – if time to market is important.
When licensing both PHY and MAC layers from the same third party (as show in Figure 5), verify that the two layers have been tested together. Find out what configurations were tested together and what methods of verification were utilized. Shipping silicon is best.
Figure 5: Synopsys DesignWare PCI Express solution
If the two layers are licensed from two different vendors, then the verification challenge is much greater. For example, in PCI Express, the majority of PHY and MAC layers communicate to each other over the PIPE interface (as defined by Intel). Although PIPE is a standard, it can be interpreted differently by different vendors. In addition, low-power functionality is not very clearly specified. These issues can lead to bugs. Thus, it is very important to understand not only the PIPE interface spec – but the implementation assumptions made by both vendors.
4.0 IP Testing and Verification
Proper validation of third party IP is usually split into two separate phases: pre-silicon and postsilicon verification.
For pre-silicon verification, the following steps may be necessary:
- Vendor IP Verification - run vendor’s provided test vectors to verify the IP. This is usually done at Verilog/VHDL RTL level and verifies that the IP delivered is functional. Synthesis can be done at this time as well, to check for any timing issues.
- Vendor IP Certification – using your own or externally purchased test vectors and test benches to verify the quality of the IP purchased by running a test suite. This independent certification may find issues on the IP itself that may have been missed by vendor’s own test vectors. This is especially important for technologies which are not mature or for IP with limited Silicon tape-outs. For PCI Express validation, tools such as Denali PureSuite greatly speed up this process.
- Vendor IP Integration – using your own vectors, verify your usage model of IP. Although the IP may be defect-free, you may be hooking up to incorrectly or using it in ways for which it was not intended. Consequently, it is very important to have sufficient test cases and test benches to thoroughly exercise all the usage modes of the third party IP.
- FPGA Verification Platform – if possible, map your entire (or subset) design to an FPGA and verify the IP on a development board. Many FPGAs currently exist which support high speed serial links (Xilinx). In addition, there are off the shelf development platforms available (Dini) which can be purchased to speed up this development. This platform can be used to verify the MAC layer and speed-up software driver development.
- Hardware Acceleration Platform – if access to Cadence Palladium/Quickturn or similar hardware acceleration is available, it may be quite beneficial to verify the design and get a head start on Software driver development by using Hardware Acceleration. Bugs are much easier to identify and correct in a Hardware Acceleration environment than in a FPGA environment.
For post-silicon verification, the following steps may be necessary:
- Serial I/O Testing – for high-speed serial links, if built-in diagnostic capabilities are not available, special testing equipment, including high-speed oscilloscopes may be necessary to verify that the quality of the PHY electrical signaling. These will be able to measure the eye-diagram, jitter, and other electrical parameters necessary for serial link certification. Figure 6 shows an example of built-in diagnostics.
- MAC Verification – to thoroughly exercise the media access layer, a number of standalone platforms are available from Catalyst and Agere. These platforms send specific test patterns to the Device Under Test (DUT) and expect a specific response. These can be used to identify MAC compatibility and certification issues, before going to PCI-SIG or some other certification body.
Figure 6: Synopsys PCI Express PHY with Built-in Diagnostics - Showing Rx Eye
5.0 IP Integration Checklist
This checklist summarizes the most important questions you should ask your IP vendor when considering high speed serial I/O’s.
|# ||Questions for the IP Vendor |
|1 ||How do I connect my IP power supplies without causing excessive jitter? |
|2 ||Do I have to space my IP apart? What can be put adjacent to the IP? |
|3 ||How am I going to test this high speed I/O? |
|4 ||The PCI Express spec has a "compliant channel" defined. How do I know if mine is? |
|5 ||Flip chip or wire bond? Does this get dictated by my IP at > 2.5Gb/s? Which is lower risk? |
|6 ||What do I need to be concerned about when I have 3 vendors who are claim they are compliant. Does that mean they are all the same? |
|7 ||At 2.5 Gb/s it is difficult to look at a signal without changing the signal. If something goes wrong, what can I do? |
|8 ||I have plans to integrate a whole bunch of high speed I/O IP. What happens if they interact in a negative way? Whose problem is it? How do I get it resolved? |
|9 ||What questions do I ask my IP vendor to ensure good yield across process corners and manufacturing variation? |
|10 ||How do I make sure I don't have ESD issues when I integrate lots of high speed IP on my SoC? |
|11 ||I have a lot of high speed I/O's on my next SoC. Power is a huge issue. How does my process selection affect the power required by the PHY? |
|12 ||I am interested in IP for both the PHY and the digital core. Does it help if they are from the same vendor? What is most important? |
|13 ||High speed IP might be running with data transitions in pSecs while PLL's spin up in uSecs. How do I manage Verilog time scales and runtimes? |
|14 ||Some high speed protocols like PCI Express have bi-directional signals and electrical idles on the outputs. How do I deal with this in Verilog? |
|15 ||My IP uses 6 levels of metal. Can I route over it? What could go wrong if I do? |
6.0 Conclusions and Recommendations
By following the recommendations outlined in this paper, the designer can avoid the common IP integration pitfalls. He can integrate third party IP, including high-speed serial links, while minimizing risk and decreasing development time. This will enable him to bring out innovative products to the market faster and with lower risk.
For more information on Synopsys DesignWare IP, visit www.synopsys.com/designware