English
Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
''Do's and Don'ts" when considering an FPGA to structured ASIC design methodology
FPGA prototyping is more successful for structured ASICs compared to standard cell ASICs when the structured ASIC mirrors the resources available on the FPGA.
By Rob Schreck, Altera
August 24, 2006 - pldesignline.com
More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast turn-around.
In a structured ASIC, the functional resources – such as logic, memory, I/O buffers – are embedded in a pre-engineered and pre-verified base layer. The device is then customized with the top few metal layers, requiring far less engineering effort to create a low cost ASIC (Fig 1). This reduces not only the time and development costs, but also the risk of design errors, since the ASIC vendor only needs to generate metallization layers. With 90-nm process technologies, structured ASICs offer the density and performance required to meet a wide range of advanced applications.
By Rob Schreck, Altera
August 24, 2006 - pldesignline.com
More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast turn-around.
In a structured ASIC, the functional resources – such as logic, memory, I/O buffers – are embedded in a pre-engineered and pre-verified base layer. The device is then customized with the top few metal layers, requiring far less engineering effort to create a low cost ASIC (Fig 1). This reduces not only the time and development costs, but also the risk of design errors, since the ASIC vendor only needs to generate metallization layers. With 90-nm process technologies, structured ASICs offer the density and performance required to meet a wide range of advanced applications.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design
- Two methodologies for ASIC conversion
- C based design methodology accelerates ASIC/FPGA design cycles
- How to get the best cost savings when implementing an FPGA-to-ASIC conversion
- FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers