Shaker Sarwary, Atrenta Inc.(08/28/2006 7:55 AM EDT), EE TimesFIFO and handshake synchronizers pose special difficulties; new tools are the answer
Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain crossings (CDCs) rank near the top in difficulty. The latest SOCs may have dozens or even thousands of clock domains, many of them difficult to verify using conventional tools such as simulation. Detecting these bugs using traditional simulation tools requires long simulation runs and a chance encounter. As a consequence, CDCs have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly re-spins.
Two particularly troublesome CDC-related issues involve FIFO- and handshake-based synchronization mechanisms. Both can be difficult or impossible to accurately verify using simulation. And conventional static CDC analysis tools do too little and too much at the same time, simultaneously overlooking realdesign errors and over-reporting large numbers of falseviolations. As a result the user is forced into an endless bug-hunting process, which often discourages the designer and leaves the real bugs undetected.
The success of static CDC verification tools is determined by two critical measures--the time taken to signoff and the completeness of CDC verification. Conventional CDC analysis tools fall short in both areas. They generate large amounts of noise (false violations)--extending the verification cycle--and provide poor coverage of complex CDC synchronization schemes.
Fortunately, a new class of CDC tool, using static analysis techniques, offers an effective automated solution to these problems. Such tools combine functional and structural analysis to both identify and verify FIFO and handshake synchronizers, while weeding out the false violations that plague traditional CDC tools.
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