English
Complex ASSP Devices: Handle increased complexity
By Andrew McGregor, Galazar Networks
Sep 18 2006 (1:35 AM), Courtesy of Network Systems Designline
Advanced telecommunications silicon integrates a wide variety of functions and interfaces to spread the high costs of device development across as many applications as possible, but this trend increases device complexity.
On the plus side this has made life easier for hardware designers who are faced with fewer problems associated with making a handful of different devices cooperate, often with semi-standard interfaces connecting them. Software designers, who typically see a more unified approach when one or two devices perform the bulk of the data path processing on a circuit card, also benefit.
The main new challenges that stem from this trend are that more sophisticated services are being demanded and the devices often contain more features than are typically required in a single application. At the same time that this sophistication is increasing, system developers are losing their ability to understand what is going on inside the silicon which is, in turn, causing development and debugging tim
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- The evolution of embedded devices: Addressing complex design challenges
- SignatureIP's iNoCulator Tool - a Simple-to-use tool for Complex SoCs
- Debugging complex RISC-V processors
- How Efinix is Conquering the Hurdle of Hardware Acceleration for Devices at the Edge
- MIPI in next generation of AI IoT devices at the edge
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Dynamic Memory Allocation and Fragmentation in C and C++
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)