by Christopher Lennard, Strategic Marketing Director ARM,
and Matthew Bellantoni, Product Marketing Manager, Carbon Design Systems
ESL is emerging as viable – indeed necessary – part of the SoC design process. The viability is being driven by the emergence and adoption of industry-wide standards. Key to enabling ESL design today is full design-chain support, with IP providers providing models of IP at the critical levels of abstraction. Only IP vendors can certify the correctness of models as validation suites are a part of the ‘crown jewels’ of the IP vendor, so supply of models to standard interfaces is absolutely critical. With the industry wide adoption of standards for ESL design – the SystemC language, the RealView® ESL APIs and the flow from ESL to implementation using the SPIRIT Consortium Specifications – we are finally able to bring the ‘ideal’ elements of ESL design into the realm of the practical.
The advent of extreme fine line processes of 130 nm or less has added many new challenges for the silicon-systems designer. On the back-end, optimizing a design to manage physical effects such as power, heat, and timing are more daunting than ever. At the front-end of the design process, implementing a System-on-Chip’s (SoC) behavior and features is becoming equally as difficult. Exploring system architectures early is now a critical part of the SoC design process to ensure that hardware and software engineers have a well specified and validated context for their design tasks. Further to this, the increasing adoption of IP from multiple sources—legacy, third-party, and newly created—means that systems integration is becoming as significant an issue in SoC design as the implementation of new design components.
With today’s complex systems we have potentially 20 million or more logic gates and multiple memories, and thousands of lines of software that need to be designed, integrated, verified for proper functionality and timing, and then validated as a complete system. The conundrum is that back-end design processes still require great detail and accuracy in the hardware design representations — that is, RTL HDL — to achieve design closure. Meanwhile the total quantity of gates in this fine- grained view overwhelms traditional simulators and makes the software integration very difficult. To address the complexity, designers are adopting new levels of design abstraction in the early parts of the design process.
The need for new levels of design abstraction is driving the rapid adoption of Electronic System-Level (ESL) design in production design flows. By adding another level of abstraction to the design flow, the designer can create an all-software virtual prototype to perform architectural exploration, profiling for performance analysis, and early software development and validation.
Enabling ESL Design Through Standards
The move to ESL design is not just another design-entry point. ESL environments enable the user to create a fast simulation model, or virtual prototype, of their system design before the detailed hardware implementation is finalized. These models can be considered part of a golden specification for the system behavior, and used throughout the design validation process as the system implementation is finalized. The early system representation provided by ESL design enables the iteration of design constraints between the hardware and software engineering tasks (See Figure 1). With embedded software becoming an evermore crucial part of a SoC architecture, this technical exchange enables the embedded software architect to become more involved in overall platform optimization.
As the system-level virtual prototype can be used as a golden model long into the hardware and software development process, it will typically contain design IP in different stages of design resolution. The system virtual prototype must support mixed levels of abstraction—from transactional level models for un-timed instruction-accurate virtual prototypes, to cycle-accurate transactional models, to RTL pin level descriptions (which are also cycle-accurate). (See Table 1)
The ability to combine multiple levels of design abstraction in one virtual prototype has several advantages. It provides a way to start the architectural analysis and software validation process earlier. It also allows the software to be validated on the actual hardware implementation model to eliminate hardware-software integration bugs earlier in the design cycle.
Unfortunately, despite these obvious advantages to the user of ESL methodologies, the ESL tools and IP market has traditionally been very fractured. This has largely been due to the lack of plug-andplay standards for ESL models and point tools, and this has inhibited adoption of the system-level design techniques. Standards, however, are now emerging, and it is critical that all tools and IP providers must consolidate on the support of these. The concept of plug-and-play for system-level design flows must support at least three technical aspects: the integration of IP models, the integration of retargetable debugging environments for the support of software development and systems validation, and the flow from ESL design to implementation design environments.
In the case of simulation model interfaces, the OSCI SystemC TLM proposal is a set of language constructs for transaction-level SystemC models. It is a useful development for the linking of system models into event simulation, such as for RTL co-simulation with ESL models. However, it does not provide a complete API for plug-andplay integration. For fast virtual prototypes taking advantage of the cycle-based abstraction paradigm, the ARM® RealView® ESL APIs have been provided openly to the industry. In the case of unified integration of debugging environments, the debugging interface of the RealView ESL APIs provides target- neutral, multicore debug integration support. Finally, in the case of linking the ESL environment into d o w n s t r e a m implementation tools, the specifications of the SPIRIT Consortium can be used. These XML system description techniques target design integration and configurability exchange moving between design environments, and interfacing of point tools and IP generators into design environments in a language neutral way.
A TLM Interface for Plug-and-Play Modeling
To integrate a system virtual prototype with IP from multiple vendors and achieve reasonable user control and visibility of that platform, the standard APIs for model integration must cover not just fast simulation, but debug and system profiling. The ARM RealView ESL APIs are the first comprehensive set of APIs for full SystemC ESL design integration encompassing all three aspects of model integration. These are provided openly to the industry by ARM, and are downloadable from the ARM website.
All ARM models that are integrated into third-party ESL environments are provided with the ARM RealView ESL APIs. The broad adoption of ARM RealView models in the industry means that support for the APIs will be widespread, and this is helping to drive a consolidation of ESL APIs across the industry. Carbon Design Systems’ SOC-VSP™ product enables designers to automatically create cycleaccurate models from RTL that comply with these RealView APIs, including the transaction, debugging and profiling interfaces.
By adhering to standard model interfaces, ESL tools can provide a way of moving quickly to fast soft prototypes that are functionally accurate, while enabling concurrent hardware and software development and integration. A virtual prototype created through ESL design can get the embedded software (ESW) development started up to 6-months earlier than traditional flows. The profiling capabilities in the tools and models allow a closer coupling of the hardware and software and give the software developers fast-running models that closely represent the final hardware, especially when the models have been created from the actual hardware implementation (RTL). The cycleaccurate models enable the design team to begin implementation of hardware-based software, which used to wait for a working hardware prototype before any significant software work could commence.
Enabling the IP Model Market
The changes in tools and methodologies are only part of the environment. Designers need models of various abstraction levels to cover the range of speed and accuracy behaviors that are a part of the development cycle. The two most important model types are un-timed or timingapproximate (instruction-based, perhaps with cycle-counting), and cycle-accurate.
The former is primarily for high-speed rapid-prototypes. The un-timed models are not used for performance benchmarking or characterization, but used as a platform for software development. The cycleaccurate models are used for benchmarking and detailed architectural exploration, and any development of “hardware aware” software.
The wide spectrum of models with varying degrees of functional and timing accuracy is required in an ESL environment, since additional accuracy in the models ultimately reduces the total throughput of the simulation. Therefore, it is important to choose the correct model for the task at hand. For example, it might make sense to use an un-timed model for a system’s CPU, while choosing a model with cycle-accurate timing for a newly developed hardware component. Any additional detail about the CPU would be wasted, while the fidelity of the newly developed component is essential. (See Figure 2)
The ability to transform models across layers of abstraction is a crucial part of the transition from an RTL to an ESL design environment, and the lack of this ability has been a substantial impediment to ESL flow adoption. Sometimes un-timed, transaction level models for IP are available, but often this is not the case. Many times only RTL is available, either from a third party or internal legacy code. The compiler component of Carbon’s SOC-VSP product creates highperformance, cycle-accurate model of RTL designs. These models can be integrated into leading ESL design and profiling tools like ARM RealView SoC Designer. This tool facilitates the transition to higher and mixed levels of abstraction by removing the manual (by hand) and error-prone translation process, while introducing simulation performance improvements.
A verifiably correct methodology
Besides tools, designers need to change other parts of their mindset, methodologies and flows. For example, to get the most out of ESL design, the design philosophy has to evolve from a design-verifyinstantiate ‘waterfall’ flow to an iterative design paradigm that incorporates an architectural exploration and optimization in parallel with design implementation. The key in any iterative design paradigm is the ability to link views together to validate their correctness in each stage of the refinement process.
Transaction level verification started as just a way to optimize transactional visualization of RTL simulation, and has advanced to true hierarchical system validation strategies. The development of transactors for linking abstract models to refined implementation is allowing ESL design environments to be directly linked into the system verification process. Furthermore, as the adoption of transactors for visualizing and controlling RTL verification advances, hardware designers will become familiar with the transactional interface concept and can move readily to more abstract modeling styles. The adoption of common interfaces for transaction level IP is helping to drive the development of standard transactors for multi-level simulation, and therefore the delivery of verification IP at the ESL level.