by Gary Ruggles, Ph.D.Director, Business Development,Physical IP, ARM
The electronics industry is in the midst of a dramatic shift away from traditional parallel communication standards and towards new, high-speed serial interface technologies. This transformation is affecting everyone in the design chain and impacts design requirements for ICs, packages, and boards as well as complete systems. This article details the standards supporting this change, challenges designers face, and some solutions available.
The industry is moving towards high-speed communications technology to meet the demands of high performance SoC designs. Two widely visible standards illustrating this trend are PCI Express (which is rapidly replacing the PCI and PCI-X busses) and Serial ATA, (which is replacing the ATA physical storage interface). Data rates for these new serial standards are pushing to 5.0 Gbps and beyond, making the design of products and systems extremely challenging.
Unlike the parallel standards they replace, the new serial standards are, for the most part, embedded clock systems. This means that no clock has to be sent along with the data from one end of a link to another. It also means that the clock must be accurately recovered from the received signal, along with the data itself. It is this difference, along with the increasing data rates, that makes serial link communications so powerful and so challenging to implement.
As standards evolve and data rates continue to climb, serial communications systems with embedded clocks will become even more dominant. These systems are scalable without limit and are free from the timing and alignment problems that limit the extension of parallel standards to ever higher bandwidths. As a result of this trend, designers are faced with new challenges as they try to successfully integrate high speed serial link technology into their products.
For all their complexity, these high speed serial links are essentially just IOs, but unlike traditional lower-speed IOs, their implementation can easily make or break a design, or differentiate one company’s product from another. To successfully integrate high speed serial links into their products engineers must overcome many challenges. The most significant by far, according to design engineers, is signal integrity (EEtimes survey - 2005). Managing signal integrity (SI) encompasses several things, including controlling signal and noise coupling, minimizing jitter, and reducing the effects of power supply and substrate noise on high speed signals. For the high data rates and low signal swings that are typical in high speed serial communications managing SI is particularly difficult, and a successful design must address SI issues at the die, package, board, and system level.
For many high speed serial standards the permissible signal swing at the receiver inputs can be below 200 mV peak-peak differential (For example, PCI Express permits a minimum differential input swing of 175 mV). At these low swings, even a relatively small amount of noise or stray signal energy can cause significant problems. For example, 50 mV of noise, a level that is often seen on power supplies, represents more than 25% of a 175 mV signal. To compound the problem, at data rates around 2.5 Gbps and above, many parts of the system begin to behave like transmission lines. As a result, traces must be designed as transmission lines and matched carefully to avoid impedance discontinuities and signal reflections. Even things like BGA bump layout and via design in the PCB become significant in determining the overall signal quality of a high speed serial link.
For the system designer, the myriad of potential SI issues all show up primarily as increased jitter and reduced jitter margin throughout the system. Jitter results in variations in the locations of clock and data edges that can lead to failures in the Clock Data Recovery (CDR) system, which in turn lead to higher Bit Error Rates (BER) and potential link failure. For many standards a BER of 10-12 is specified as the minimum acceptable level of performance, and this BER must be met for any link established between a compliant transmitter and receiver. When a given transmitter and receiver are able to establish a link and transfer data with a BER at or below that required by the standard they are considered to be interoperable.
Interoperability is one of the key factors determining the success and versatility of a serial link product. For this reason, many standards bodies now hold regular “Plugfests” to assess and document the interoperability of serial link products from various vendors. One of the best ways to maximize interoperability and improve system performance is to provide extra jitter margin at both the transmit and receive ends of the high-speed data link.
Figure 1: ARM PCI Express PHY Transmit Eye for PRBS31 pattern (shown without pre-emphasis)
At the transmitter, this means minimizing the amount of jitter on the high speed serial data output. To achieve this ARM’s 90 nm and 65 nm serial link PHYs have been designed using a PLL based on a LC tank oscillator rather than the conventional ring oscillator found in most designs. An LC tank oscillator-based PLL has inherently lower phase noise than other designs resulting in more stable clock edges and reduced jitter. As an example, the PCI Express standard allows for a maximum transmit jitter of 0.25UI, or 100pS peakpeak at 2.5 Gbps. The ARM VSL210 PHY for PCI Express generates less than 0.15UI of jitter under worst case conditions, and typically generates less than 0.1UI. Figure 1 illustrates the excellent jitter performance of the ARM PCI Express serial link transmitter. The figure shows a transmit eye for both 2.5 Gbps (Gen 1) and 5.0 Gbps (Gen 2) operation with a PRBS31 pattern. In the figure the pre-emphasis has been turned off to more clearly illustrate the extremely low jitter achieved with the LC tank VCO design.
At the receiver, achieving better jitter margin means the receiver must tolerate greater levels of jitter on the incoming data signal. This can be achieved by a combination of good receiver design and the use of equalization. In a system, equalization can be used to overcome the Inter Symbol Interference (ISI) that results from dispersion and attenuation of high speed signals through the channel. Equalization can be applied to either the transmitted signal, to the received signal, or both. To achieve the best performance possible a receiver should include some form of equalization to boost the high frequencies that are lost during transmission through the system channel, because transmitter pre-emphasis alone may not be sufficient in all systems, and pre-emphasis typically consumes more power than receiver equalization. In most serial link designs the receiver uses clocks generated by a PLL—often the same PLL as used for the transmitter. More stable clock edges (less jitter) on the clocks for the receiver thus results in increased jitter tolerance. By using the same LC tank based PLL for the receiver clocks, combined with a programmable liner equalizer in the receiver, ARM’s solution achieves a very high level of jitter tolerance, greater than 0.8UI at worst case conditions, and as high as 1.0UI for typical conditions. Figure 2 shows and example of how receiver equalization can be used to overcome complete eye closure due to ISI and achieve error free data reception.
Figure 2: Receive eye for ARM VSL230 PHY operating at 6.25Gps before and after application of receiver equalization, showing ability to open a completely closed eye and achieve 1.0UI + of jitter tolerance.
Since the total jitter budget of a high speed serial communication is divided among all the components in the system, less jitter at the transmitter means that the jitter tolerance requirements at the receiver can be relaxed while still achieving error-free data transmission. The ARM solution, with its very low transmit jitter, will therefore interoperate with a wider range of receivers, even those with poor jitter tolerance. Similarly, because of the high jitter tolerance of the ARM serial link receiver, even poor transmitters can be accommodated with acceptable bit error rates.
Noise Immunity in Large SOCs
Another source of jitter than can affect interoperability and system performance is noise that couples into the data signal. This noise can come from coupling of adjacent high speed data lines, but this can be controlled by the use of good standard design practices in the PHY, package and board designs. Within the PHY, this means using fully differential circuits for all the high speed signal paths. Differential circuits are virtually immune to common mode noise coupling and result in a transceiver design with reduced sensitivity noise coupling. ARM uses fully differential circuits in the transmitter, receiver and PLL to minimize common mode noise coupling and reduce system jitter.
Another source of noise that can be more difficult to control is noise that comes from millions of digital gates switching in an SOC. This can show up as power supply noise or as noise injected into the substrate of the die. A good PHY design must be able to operate in the presence of this type of noise if it is to be used in an SOC design. Power supplies are typically regulated at the board level, but additional regulation inside the PHY can be advantageous. The most sensitive circuit in a serial link is the VCO used in the PLL, so regulating this power supply can provide added noise immunity resulting in reduced jitter. The ARM serial link designs include a voltage regulator inside that supplies the VCO block with a clean source of power, thereby minimizing the effects of power supply noise on jitter and jitter tolerance. Additional immunity to substrate noise injection can be achieved by use of a guard ring, or junction isolation ring that protects the PHY from the digital core of the SOC. When using an ARM PHY, no additional guard ring or junction isolation is required, since it is already included as part of the macro itself.
The successful integration of a high speed serial link IP into an IC design involves overcoming several challenges to achieve a design with low transmit jitter, high receiver jitter tolerance and good system interoperability. Managing the various sources of noise and handling signal integrity issues correctly are key to success. While many issues need to be addressed at the package, board and system level, the right PHY design is critical and can be the difference between a robust, high-yielding, successful design with good interoperability, and one that just meets the minimum specifications of the standard.
For more information on ARM Velocity PCI ExpressVelocity PCI Express PHY Series and other physical IP, SATA and other PHY IP, please contact ARM at firstname.lastname@example.org or visit our web site at www.arm.com