By Neeraj Parik, Xilinx, Corp. October 02, 2006 - networksystemsdesignline.com
Focusing on such standard parallel PHY interfaces for Gigabit Ethernet as RGMIIv2.0, RGMIIv1.3, and GMII, here is an analytical approach showing how to transform timing specs to design constraints, and a methodology to verify adherence to timing specs using HDL-based timing simulation.
While completing any FPGA or ASIC design, it is very important to verify the conformance of the off-chip interface timing to the standard specifications. If the design uses proprietary interface(s) a detailed timing specifications must be developed and adhered to. Once the timing specifications are known, a methodology is required to simulate and verify the design conformance to the specifications.
Gigabit Ethernet, popularly referred to as GigE, was ratified by IEEE in 1998 under the name 802.3z. GigE supports only point-to-point configurations, unacknowledged datagram service (fire and forget) with both unicast and multicast addressing. GigE supports full"duplex (used in switching) as well as half-duplex (connected to hub) mode of operation. Maximum length of wire in Ethernet is determined by signal strength in full-duplex mode and minimum packet length in half-duplex mode. There have been several extensions to fast Ethernet such as "carrier extension" to increase peripheral distance of operation in half-duplex from 25 meters to 200 meters; also added was the "frame bursting" to effectively utilize link efficiency with extended minimum packet size. GigE specifies use of pause frames as flow control mechanism. These pause frames allow the transmitter to pause in units of 512 ns up to maximum of 33.6 ms.
GigE supports fiber (single-mode and multi-mode) and copper cabling (1000 Base-CX and 1000 Base-T). GigE uses 8B/10B encoding for 1000 Base-X (comprising of 1000 Base-LX, 1000 Base-SX and 1000 Base-CX) with effective signaling rate of 1.25Gbps. 1000 Base-T scrambles each byte in the MAC frame to randomize the bit sequence before it is encoded using a 4-D, 8-State Trellis Forward Error Correction (FEC) coding. The 1000 Base-T uses four pairs of category-5 UTP to allow four symbols to be transmitted in parallel. Each symbol is encoded using five voltage levels (using Phase Amplitude Modulation-5 signaling; the fifth level is used for FEC coding, which enhances symbol recovery in the presence of noise and crosstalk.) representing 2 data bits. These four pairs transmit 8 bits at a time, operating at 125 MHz.
GigE uses the standard OSI model architecture and separates the physical layer from the data link layer. The physical layer is concerned with transmitting raw bits over a communication channel. The design issues at the physical layer deals largely with the mechanical, electrical and timing interfaces of the Physical medium. The GigE data link layer takes care of framing (breaking input data into chunks of few thousand bits) and flow control using pause frames. There is no error handling at the GigE data link layer. Frames received in error are dropped, relying on higher layers (e.g. TCP) to provide reliable transmission. The data link layer is also referred as MAC layer.
There are several standard specifications to transfer the frames between the PHY and data link layer. The standard protocols provide the mechanism to signal transmit enable, transmit frame error, received error and receiver sense either as separate or multiplexed signals. In this article we focus on the most popular parallel standards i.e. GMII, RGMII v1.3, RGMII v2.0. All these GigE parallel PHY interfaces are source synchronous, operating nominally at 125MHz. We discuss each of the above mentioned interfaces, one by one.
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