By Warren Savage, IPextreme, Inc.
October 01, 2006 -- edadesignline.com
The EDA industry has provided designers with a vast arsenal of tools that can be used to verify the functional correctness of an IP design.
Functional correctness for IP is essential yet elusive. In our first article A hierarchy of needs for SoC IP reuse, we described a hierarchical model to relate the relative priority of the deliverables from IP providers to the SoC designer who uses them. Based on Abraham Maslow's theory that all human beings have a basic set of needs that form a hierarchy, the SoC Designer's IP Needs Hierarchy has five levels of needs beginning with Functional Correctness:
1. Human beings have an inherent hierarchy of needs that must be satisfied in order.
October 01, 2006 -- edadesignline.com
The EDA industry has provided designers with a vast arsenal of tools that can be used to verify the functional correctness of an IP design.
Functional correctness for IP is essential yet elusive. In our first article A hierarchy of needs for SoC IP reuse, we described a hierarchical model to relate the relative priority of the deliverables from IP providers to the SoC designer who uses them. Based on Abraham Maslow's theory that all human beings have a basic set of needs that form a hierarchy, the SoC Designer's IP Needs Hierarchy has five levels of needs beginning with Functional Correctness:
In this article, we discuss the most basic need of every chip designer – functionally correct IP. The best and most unambiguous measure of functional correctness is the extent to which IP has been validated in production silicon. SoC designers don't like being the lab rats of IP providers and often find themselves discovering bugs that should have been sorted out long ago by the provider. SoC designers want to use IP that has been silicon proven – and the more times the better.