Fit the hardware to the algorithm with SystemC models

By Bo Wu, CoWare, and Jens Reinecke, RWTH Aachen University, Germany

Learn how to model DSP algorithms in SystemC without being a SystemC expert. These models facilitate hardware/software partitioning, and allow you to consider communication and memory architectures when designing your algorithm. These models also ease software development and hardware verification.

System-on-chip (SoC) designs commonly consist of one or multiple processors (e.g. DSP or reduced instruction set computing (RISC) processors), interconnects, memory sub-systems, DSP hardware accelerators, and peripherals such as direct memory access (DMA) controllers and memory management units (MMU). In order to cope with the complexity of such a design, engineers must perform several recurring design tasks. These include creation of an executable specification, architecture exploration, embedded software development, and hardware-software verification.

The traditional design flow is a sequential flow, where all design stages are separated. The algorithm designer finishes his or her work and delivers models of the DSP system and specifications to the hardware designer and the embedded software developer. Starting from these specifications, hardware and software development begins—almost from scratch—without the further benefit of the algorithm designer's experience. It is obvious that this traditional flow has many disadvantages including:

The software developer has to wait for a first hardware prototype to implement his tasks.
The software developer cannot take hardware features into account until late in the design process. This is unacceptable, because interconnects and memory architectures should be taken into account early in the design process. At minimum, they should be considered when partitioning the algorithm into hardware and software components. The algorithm designer might even need to take them into account when defining functional modules.
The entire platform can be tested sufficiently only the first prototype is ready. Consequently, problems or inefficiencies are identified late in the design process. This can lead to a need to rebuild the prototype, a compromise in system performance, or even a re-spin of the chip.

These problems can be avoided by involving the algorithm designer in the early stages of the architecture design. This is enabled through electronic system level (ESL) design approach. In order for designers to accept an ESL-based approach, there must be an efficient and intuitive methodology for modeling complex platforms. This article introduces such an approach using a SystemC-based virtual hardware platform methodology.

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