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How to utilize advanced FPGA features without getting locked into an architecture
By Roger Do, Mentor Graphics
October 18, 2006 -- pldesignline.com
A vendor-independent design approach that allows design development independent of the target FPGA architecture can pay big dividends.
Programmable logic in today's FPGAs now provides more than just basic glue logic. Advanced features that accommodate your system needs and offer the flexibility for design verification and debugging, such as large complex memory and DSP structures, have been implemented in embedded blocks in the FPGA. Each major FPGA vendor offers competitive devices with slightly different specifications and characteristics that can affect both functionality and performance of a target design. For example, while devices from two different vendors may both be optimized for DSP applications, small details in how the registers are pipelined or how the data is muxed can affect the overall performance and utilization of the DSP function. A design approach that allows design development independent of the target FPGA architecture can pay big dividends.
In a vendor-independent approach, hardware description language (HDL) can be written to allow multiple FPGA architectures to be targeted without code modification and re-simulation. This approach allows you to fully explore the design space, delaying the selection of the FPGA architecture until the implementation phase. The resulting design is easier to maintain and retarget should the vendor obsolete the original FPGA. Furthermore, such an approach allows for easy reuse of functional blocks by other projects as the source code remains independent of architecture.
With a vendor-independent design methodology and a capable synthesis tool, the ability to select the best device for your design allows you concentrate on the design and not on whether you have chosen the correct device. Synthesis technology provides the ability to seamlessly implement complex functions in the design by automatically inferring or recognizing complex structures and properly mapping them to the available resources in the target FPGA technology.
October 18, 2006 -- pldesignline.com
A vendor-independent design approach that allows design development independent of the target FPGA architecture can pay big dividends.
Programmable logic in today's FPGAs now provides more than just basic glue logic. Advanced features that accommodate your system needs and offer the flexibility for design verification and debugging, such as large complex memory and DSP structures, have been implemented in embedded blocks in the FPGA. Each major FPGA vendor offers competitive devices with slightly different specifications and characteristics that can affect both functionality and performance of a target design. For example, while devices from two different vendors may both be optimized for DSP applications, small details in how the registers are pipelined or how the data is muxed can affect the overall performance and utilization of the DSP function. A design approach that allows design development independent of the target FPGA architecture can pay big dividends.
In a vendor-independent approach, hardware description language (HDL) can be written to allow multiple FPGA architectures to be targeted without code modification and re-simulation. This approach allows you to fully explore the design space, delaying the selection of the FPGA architecture until the implementation phase. The resulting design is easier to maintain and retarget should the vendor obsolete the original FPGA. Furthermore, such an approach allows for easy reuse of functional blocks by other projects as the source code remains independent of architecture.
With a vendor-independent design methodology and a capable synthesis tool, the ability to select the best device for your design allows you concentrate on the design and not on whether you have chosen the correct device. Synthesis technology provides the ability to seamlessly implement complex functions in the design by automatically inferring or recognizing complex structures and properly mapping them to the available resources in the target FPGA technology.
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