By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies, Inc., Nov 20 2006 (9:10 AM), Embedded.com
Designers everywhere face ever increasing constraints on system cost and power consumption, while at the same time being required to add more performance and functionality to their designs. This is a difficult trade-off to address successfully.
Some previous approaches have been to ramp up the clock speed of a processor, but this usually results in increased power consumption. Additionally, memory performance has not kept pace with processor technology (see Figure 1, below), and this mismatch limits any significant gains in system performance. Consequently the higher-frequency approach has led to diminishing returns.
|Figure 1 Processor-memory mismatch causes system performance bottlenecks |
A multi-core system is another option, but this suffers from a larger die area and higher cost. Any increase in performance comes at a fairly substantial cost in silicon and system power consumption. Multiple-issue processors with two or more execution units offer another option, but they struggle to make best use of hardware resources, and also have an area penalty. Additionally, the software has to be revised in many cases to make best use of the multiple pipelines.
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