English
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies
Nov 27 2006 (0:30 AM), Embedded.com
The key to the Virtual Processor Element (VPE) approach used in the MIPS 34K core is a set of extensions of the processor's basic instruction set architecture, rather than a specific set of hardware features to enable efficient multi-threading. In the case of the 34K core, the MT ASE is an application-specific extension of the MIPS32/MIPS64 instruction set and privileged resource architecture, meaning that it is a true architectural superset.
In the light of all this, the MIPS MT ASE strives to provide a framework both for the management of parallel threads on the same CPU and for the management of parallel threads across multiple cores, and indeed for the migration of threads from one multi-threaded processor to another.
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