English
How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time
By Ralph von Vignau, NXP Semiconductors
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
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