English
How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time
By Ralph von Vignau, NXP Semiconductors
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Integrating 'hard' IP into a system-on-chip
- Case study of a complex video system-on-chip
- How effective use of ESL tools can increase your HW/SW system design productivity
- A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
- Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment
New Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Maximizing ESD protection for automotive Ethernet applications