By Christopher Ebeling and Harmeet Bhugra, Optical Internetworking Forum (OIF) December 18, 2006 -- networksystemsdesignline.com
SPI-S delivers a channelized, streaming-packet interface scaleable to hundreds of Gb/s for chip-to-chip and backplane applications using OIF CEI interconnects with either 64B66B or CEI-P framing. By leveraging existing FPGA and ASIC SERDES technology SPI-S will not require new development for its physical interface.
As overall bandwidth throughput increases, selecting the right chip-to-chip interface becomes critical for such systems as switches, routers, etc. So far, Optical Internetworking Forum's (OIF) System Packet Interface (SPI) 4.2 is the most widely deployed chip-to-chip interconnect for high-speed data paths. The System Packet Interface--Scaleable (SPI-S) is the next-generation interface developed by the OIF to take advantage of serialization of physical interconnects. Figure 1. System Block Diagram showing SPI-S
The SPI-S effort was jointly started by the Network Processor Forum (NPF) and OIF in summer 2004. Since then, NPF and OIF have merged and the OIF Physical Link Layer (PLL) group took over the development of the SPI-S interface. The OIF is an industry group comprising of over 100 system vendors, carriers and silicon vendors. The OIF recently approved the SPI-S implementation agreement for publishing after almost two years of development.
Early on the members of the NPF and OIF recognized that the number of pins on application-specific standard products and network processors was experiencing rapid growth. The wider parallel interfaces were causing problems on the board (i.e. routing and lane to lane skew). Traditional high-speed interconnects used to transfer chip-to-chip data have transitioned to serial interconnects. As a result, the OIF and NPF partnered to define a SPI-like interface, providing a significant performance boost with considerable technology reuse based on an industry standard Serial I/O Block. After taking an exhaustive look at the physical I/O available at that time, the group decided to base the interface on OIF's CEI (Common Electrical Interface) physical I/Os. This resulted in a significant reduction in pin-count. For example, pin count for a 10G interface configuration could be reduced from 80 pins for SPI 4.2 to eight pins using CEI 6.25G, and four pins using CEI 11G links. Refer to Figure 2 for a comparison. Figure 2. Pin comparison for 10 Gbps link
The objective for SPI-S was to define an evolutionary, high speed, scalable SPI that could efficiently transfer common packet formats, such as Ethernet packets ( 64 bytes), ATM cells (48 or 52 bytes), IP packets ( 40 bytes) and Control packets (6 to 10 bytes for NPF Messaging).
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