Top 10 methods for ASIC power minimization -- Part 1

By Andreas Olofsson, Analog Devices
January 08, 2007 -- powermanagementdesignline.com

This is a two-part article focusing on power minimization in deep submicron ASICs.

Part 1 list five of the ten and is dedicated to technology independent architectural power saving techniques and basic power consumption theory. Part 2 focuses on power saving techniques at the implementation level.

The physical limits of CMOS technology scaling and the ever increasing number of on-chip features is causing low power design to move from being one of many design metrics to being the number one design metric. Some authors have written "doom and gloom papers" proclaiming the end of Moore's law due to the inability to scale down power as we move to 65 nm and below. While there is some truth to this, a counter claim could be made that that the VLSI design community is still lagging in its application of low power design techniques and that the fundamental show stopper is still a ways out. Considering that many of the low power techniques that are starting to be employed today were invented 10 to 20 years ago, there is still plenty of space at the bottom. The goal of this article is to summarize the most effective low power techniques available today and to highlight some of the challenges that lie ahead.

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