Video and image processing design using FPGAs
January 12, 2007 -- videsignline.com
FPGAs eliminate the up-front non-recurring engineering costs and minimum order quantities associated with ASICs, and the costly risks of multiple silicon iterations through the capability to be reprogrammed as needed during the design process.
Innovations such as HDTV and digital cinema revolve around video and image processing and the rapid evolution of video technology. Major advances in image capture and display resolutions, advanced compression techniques, and video intelligence are the driving forces behind these technological innovations. At the same time, rapid change in standards and higher resolutions are pushing designers away from off-the-shelf technology.
Resolutions in particular have increased dramatically in just the last few years. The following table illustrates current state-of-the-art resolutions in different end types of applications.

Table 1: Resolutions by Application Types
The move from standard definition (SD) to high definition (HD) represents a 6X increase in data needing to be processed. Video surveillance is also moving from the Common Intermediate Format (CIF) (352 x 288) to the D1 format (704 x 576) as a standard requirement, with some industrial cameras even moving to HD at 1280 x 720. Military surveillance, medical imaging, and machine vision applications are also moving to very high resolution images.
Related Articles
- Video and image processing design using FPGAs
- Designing low-power video image stabilization IP for FPGAs
- Using vector processing for HD video scaling, de-interlacing, and image customization
- Artificial Intelligence and Machine Learning based Image Processing
- Image Processing - RTL Implementation of Median Filtering for Image Denoising
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |