Defining the TLM-to-RTL Design Flow
(01/15/2007 12:30 PM EST) -- EE Times
As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron implementation technology have semiconductor and system companies searching for new electronic system level (ESL)-based design flows.
An emerging trend is a transaction level modeling (TLM)-to-register transfer level (RTL) design flow, though a set of requirements needs to be addressed to ensure a successful transition to this new flow.
This article uses the generic term TLM to refer to a higher abstraction level model. Where necessary, it will be prefixed with cycle-accurate, cycle-approximate or functionally accurate to denote the accuracy level.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
New Articles
- Mastering Key Technologies to Realize the Dream - M31 IP Integration Services
- Create high-performance SoCs using network-on-chip IP
- IoT Security: Exploring Risks and Countermeasures Across Industries
- How Efinix is Conquering the Hurdle of Hardware Acceleration for Devices at the Edge
- An overview of Machine Learning pipeline and its importance