By Toshinao Matsumura, InventureJanuary 18, 2007 -- edadesignline.com
In designing the high-speed interconnect core Z-core InterConnect MIIX, engineers at the Zuken SoC Design Center (now known as Inventure) decided that system performance could be increased using split transaction technology in the inner bus. During the evolutionary transition from PCI to PCI Express, the split transaction concept was adopted for Inventure's Z-core PCI Express. In short, split transaction enables command execution before the response to the previous command. The split transaction technique spread from the CPU world to the system bus world such as PCI Express, and subsequently was adopted for use in the inner bus.
During its initial research the team discovered that the OCP standard already contained split transaction capability. Inventure did not implement the entire OCP standard, but made use of many parts of the OCP throughout the design process. The Inventure MIIX interconnect and the OCP standard are focused on improving overall system performance.
MIIX provides high-speed interconnection using the split transaction feature available in OCP2.0. Through an easy to use GUI, designers can customize MIIX. Inventure is providing "platform IP", where several different IP cores are combined in a pre-configured fashion with an OCP based interconnect, to provide a complete System-On-Chip design solution. The MIIX interconnect serves as the backbone for this platform IP concept.1. OCP based interconnect core used as a backbone of a platform IP
OCP is a complete synchronous type interface standard established by OCP-IP for the purpose of providing plug-and-play IP design. The specification, available at www.ocpip.org
without charge provides a strict definition of interfaces to easily connect each IP. Designers can freely configure OCP in accordance with the characteristic features of their own IP. Designers can implement an optimum interface circuitry with the required signals by utilizing only the necessary bit width.. OCP is often seen as an extension of other bus protocols such as AHB, but OCP is an interface standard not a bus standard. It allows for a one-on-one connection between OCP Master and an OCP Slave. If designers desire to make multiple connections, an interconnect module is required.
When Inventure began the project, focus was placed on the following: criteria:
- The IP should be simple, high-performance and low latency. To achieve this, the IP is configured without inner memory to satisfy both latency and throughput.
- Must make use of the new burst model in OCP version 2.0, which includes the use of Single Request Multiple Data (SRMD) bursts, which can be used to achieve packet-like transaction. In addition, use the reqdata_together configuration parameter to simplify the OCP protocol phases, by forcing the OCP request and datahandshake phases to take place during the same cycle avoiding unnecessary precedent issuance of the write commands.
- Users should be able to easily predict at the system design level how their designed system will perform. In other words, MIIX is not intended to be multifunctional but rather high-performance.
- User friendly IP. The user can easily customize and debug through GUI.
- High connect ability to Inventure's existing PCI Express IP.
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