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Using PCIe in a variety of multiprocessor system configurations
By Jack Regula, PLX Technology
Jan 22 2007 (0:15 AM), Embedded.com
PCI Express (PCIe), like the legacy PCI bus it evolved from, was architected to serve as a simple DMA I/O subsystem for a single host processor.
And like PCI, it's already being used in a much wider variety of applications and usage models, many of which require support for multiple processors. Not long ago, only the non-transparent bridge was available to address this need, but there are now a number of alternatives available.
Address-translation capabilities now available in some root complexes make the crosslink at least marginally useful for host-to-host communications. Additionally, there are now embedded processors with native PCIe interfaces that, in effect, include a non-transparent bridge.
Furthermore, on the horizon is PCI-SIG standard for multi-root shared I/O and multi-root I/O virtualization called MR IOV, which is easily extended to support host-to-host communications.
Jan 22 2007 (0:15 AM), Embedded.com
PCI Express (PCIe), like the legacy PCI bus it evolved from, was architected to serve as a simple DMA I/O subsystem for a single host processor.
And like PCI, it's already being used in a much wider variety of applications and usage models, many of which require support for multiple processors. Not long ago, only the non-transparent bridge was available to address this need, but there are now a number of alternatives available.
Address-translation capabilities now available in some root complexes make the crosslink at least marginally useful for host-to-host communications. Additionally, there are now embedded processors with native PCIe interfaces that, in effect, include a non-transparent bridge.
Furthermore, on the horizon is PCI-SIG standard for multi-root shared I/O and multi-root I/O virtualization called MR IOV, which is easily extended to support host-to-host communications.
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