By Sergio R. Ramirez and Shawn McCloud, Mentor GraphicsMar 1 2007 (1:00 AM) -- Embedded Systems Design
During the last few years, the performance and capacity of field programmable gate arrays (FPGAs) has increased dramatically. At the same time, the cost of performing the basic digital signal processing (DSP) operations, such as multiply and add, per unit of time in FPGA chips has decreased dramatically.
During the same period, synthesis tools have evolved to the point where complicated DSP modules and even complete subsystems can be described in a high-level language such as C++. These tools take the high-level description and synthesize it into an ASIC or FPGA, which is tailored to the performance requirements of the design's implementation.
The convergence of these two technologies has opened some opportunities for designers. First, FPGA implementations of DSP designs become competitive with respect to dedicated digital signal processors and custom ASICs. And second, electronic system level (ESL) technology enables the designer to take advantage of this competitiveness to produce a finished design in a short time. This increased productivity reduces the nonrecurring engineering costs, further increasing the design's competitiveness.
Any given DSP algorithm specifies a number of basic DSP operations to be performed. In a dedicated DSP integrated circuit, the computation is performed serially, therefore, the number of operations and the clock speed at which the chip runs determines the time required to perform an algorithm. In an FPGA implementation, if the algorithm allows it, however, the algorithm can be parallelized in a number of execution units, which are tuned to the needs of the algorithm being implemented. Figure 1 shows two possible implementations of a finite impulse response (FIR) filter. The first implementation is the only possible one in a dedicated DSP chip. Note that the low-performance/low-parallelism implementation as well as the high-performance/high-parallelism implementation--and many implementations in between--are available to the FPGA designer.
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