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1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
How to map the H.264/AVC video standard onto an FPGA fabric
By Wilson Chung, Xilinx Inc.
March 02, 2007 -- dspdesignline.com
Despite its promise of improved coding efficiency over existing standards, H.264/AVC still presents engineering challenges.
It incorporates the most significant changes and algorithmic discontinuities in the evolution of video coding standards since the introduction of H.261. As a result, to achieve a real-time H.264/ AVC encoding solution, multiple FPGAs and programmable DSPs are often used.
To illustrate the computational complexity required, let's explore the typical runtime-cycle requirements of the H.264/AVC encoder based on the software model provided by the Joint Video Team (JVT). Using Intel VTune software running on a Pentium III 1GHz CPU with 512Mbytes of memory, achieving H.264/AVC SD with a main profile encoding solution would require about 1,600 billions of operations per second.
March 02, 2007 -- dspdesignline.com
Despite its promise of improved coding efficiency over existing standards, H.264/AVC still presents engineering challenges.
It incorporates the most significant changes and algorithmic discontinuities in the evolution of video coding standards since the introduction of H.261. As a result, to achieve a real-time H.264/ AVC encoding solution, multiple FPGAs and programmable DSPs are often used.
To illustrate the computational complexity required, let's explore the typical runtime-cycle requirements of the H.264/AVC encoder based on the software model provided by the Joint Video Team (JVT). Using Intel VTune software running on a Pentium III 1GHz CPU with 512Mbytes of memory, achieving H.264/AVC SD with a main profile encoding solution would require about 1,600 billions of operations per second.
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