English
A Simple New Approach to Hardware Software Co-Verification
By Ernst Zwingenberger, El Camino GmbH
Mar 5 2007 (1:30 AM), Embedded.com
Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach.
However, implementing a coverage-driven verification environment in a system-level environment requires developing a sequence library, which has proven to be a time-consuming task.
To configure, or reconfigure the library, requires planning for and testing a huge number of interactions with the various portions of the device under test. The challenge poses a significant bottleneck in the verification process of a complex system or device.
A recent project of one of our customers provides a great example. One of their SoCs for use in an HDTV system presented some serious complexity. The SoC included a CPU subsystem, memory manager, and multiple bus interconnects. To test the subsystem, we were looking at more than 6000 register fields - a potential verification bottleneck to say the least.
Mar 5 2007 (1:30 AM), Embedded.com
Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach.
However, implementing a coverage-driven verification environment in a system-level environment requires developing a sequence library, which has proven to be a time-consuming task.
To configure, or reconfigure the library, requires planning for and testing a huge number of interactions with the various portions of the device under test. The challenge poses a significant bottleneck in the verification process of a complex system or device.
A recent project of one of our customers provides a great example. One of their SoCs for use in an HDTV system presented some serious complexity. The SoC included a CPU subsystem, memory manager, and multiple bus interconnects. To test the subsystem, we were looking at more than 6000 register fields - a potential verification bottleneck to say the least.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- A New Methodology for Hardware Software Co-verification
- IP Verification : RTL prototyping: a hardware/software co-verification solution
- Hardware/Software Co-verification in a System LSI Design
- Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform
- Approaches to accelerated HW/SW co-verification
New Articles
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
Most Popular
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Design Rule Checks (DRC) - A Practical View for 28nm Technology