English
A High-Performance Platform Architecture for MIPS Processors
Jack Browne, vice president, marketing
MIPS Technologies, Inc.
Mountain View, California USA
Abstract:
Sustaining high processor performance in real-world applications requires careful SoC architecture. For example, an L2 cache may be needed to minimize memory latency, especially for single-threaded processors; additionally, a high-performance non-blocking interconnect fabric is often essential to avoid data transfer bottlenecks.
With time-to-market pressures mounting for complex 90nm and 65nm SoCs, MIPS Technologies and its partners can now offer fully verified platform architectures and supporting environments. This presentation will provide insight into a new high-performance platform architecture for MIPS-Based™ SoCs. A key goal is to allow high peak processor performance to be sustained for real-world applications which – unlike Dhrystone– include cache miss, interlock stalls and interrupts.
The platform architecture will be implemented with both new MIPS designs as well as partner IP with all platform implementations fully verified by MIPS Technologies. The architecture allows MIPS processors to sustain high performance under realistic workloads. MIPS customers will also benefit with improved time-to-market. The platform architecture provides numerous configuration options to support the wide variety of SoC requirements.
This presentation will also outline the ESL tools required to support performance analysis for proper selection among the numerous platform configurations as well as software debug.
Why use Platforms?
The concept of platform-based design for SoC and embedded systems is rapidly gaining traction among platform vendors and users.
Vendors appreciate the following advantages:
In embedded systems, there are SoC Platforms produced by the semiconductor vendors, IP Platforms offered by IP vendors and Software Platforms from vendors in the embedded software market.
SoC Platforms
In the SoC world, most platform discussion revolves around using SoC platforms as a methodology to design a family of semiconductor products. The SoC platform chip is a product that results from using a platform-based methodology.
Figure 1 A MIPS-Based™ Digital Video Platform
Figure 1 shows a Digital Video Platform from Philips based on the Nexperia Platform. Beyond the MIPS core, additional functionality is required for the application. Some of this is common industry-standard I/O and other peripherals, but much application-specific IP is required as well. In addition, the vendor provides a great deal of functionality in the form of software, supplying or enabling the software development tools to use with the platform. The SoC is only part of what the vendor must offer the OEM customer. Normally, they must provide a reference design based on the SoC.
Figure 2 TI's OMAP ARM-based platform
Figure 2 shows TI’s OMAP platform. Like the Nexperia platform, this is a dual processor system and, again, TI has had to add considerable additional IP beyond the licensed ARM core.
As well as the main SoC chip, there is usually much other functionality supplied in support chips from the platform vendors and other suppliers.
IP Platforms
In contrast to the SoC platforms developed by semiconductor vendors, IP platforms tend to be much less comprehensive and are usually market-specific as opposed to application-specific.
The ARM PrimeXsys platform, originally developed as a wireless platform, is an extension of their business of supplying IP components for use with the ARM processor core.
Figure 3 An IP Platform
Software Platforms
While not the primary topic of this paper, software platforms play an important role in the design of embedded systems. This type of platforms usually consists of an RTOS or OS, middleware, application specific software and the development tools for use with the platform.
Figure 4 Wind River's Consumer Devices Platform
An example of this type of platform is shown in Figure 4. This is a software platform that is not application-specific, but has the common functions used in the design of consumer devices.
Requirements for an IP Platform
The IP components for a platform (and for SoC Design, in general) must be available in forms that allow its integration into an SoC design flow. This means supporting the common EDA design flows and modeling the IP at different levels of abstraction.
Synthesizable IP Platform
An IP Platform must have components that are available as RTL. A synthesizable platform is the combination, in RTL Verilog, of the semiconductor IP components. The platform must be configurable to allow the user to add, modify and delete components. The RTL must also contain the necessary support and scripts to be synthesizable using commercially available tools. A configurable test bench that allows the user to run verification tests on his particular configuration is also part of the platform. This level of abstraction is what a semiconductor or SoC vendor ultimately would develop or license from an IP company, to perform his SoC design.
There are platform building tools for this type of platform available from companies such as Mentor Graphics and Synopsys.
The SPIRIT consortium has defined a format for describing the components and these tools allow platforms to be built from components that are specified using the SPIRIT format.
System-Level/Virtual Platform Modeling
A system level model is a functionally accurate and/or timing accurate component that models the behavior, timing and interfaces of some or all of the components of the platform and provides control and visibility of the internal state of the hardware. These models provide cycle and timing accuracy or timing-close accuracy and are written in System C, C/C++ or a derivation thereof, and these will then run much faster than the source RTL or gate-level simulation. The modeling of the system may use transaction-based modeling to describe the interaction of components with a staged progression to more and more accuracy. The Open SystemC Initiative (OSCI) has defined transaction level modeling specifications for SystemC models.
At a higher level of abstraction, this type of modeling commonly involves virtual platforms. They are configurable or fixed simulation platforms that can run with real operating system images and real application software. Each virtual platform is an executable representation of the components of a SoC platform. It runs on a host workstation under the control of an application on the host machine. The modeling concentrates on the functionality or behavior of the system and sacrifices timing accuracy for performance. This approach allows operating systems to boot and run with reasonable response times. It allows applications, device drivers and sometimes OS ports to be developed. The models are normally written in C/C++, System C or some language designed especially for this purpose.
In addition to emulating the ‘internal’ components of the system, a virtual platform also emulates the external devices connected to the peripheral interfaces. This can include memory, hard disks, terminals, switches, LEDs, keyboard, mouse and displays. In some cases, the Virtual Platform may connect virtual components to real components on the host system. For example, the keyboard input comes from the host’s real keyboard.
Tools for system-level/virtual platform modeling
are available from the major EDA and ESL vendors including CoWare, Mentor Graphics, Summit Design, Synopsys and VaST.
Physical Platforms
Physical platforms normally take the form of a development board containing the components in a chip or an FPGA. Real devices such as keyboards, displays, hard disks, etc., connect to provide a single board computer running an operating system or monitor. A prototyping area, normally utilizing FPGAs, is available for expansion of the platform. In addition, external I/O buses, such as PCI-Express, make the platform expandable for vertical applications or debug use. If the design is transferred to an emulation system from vendors such as Cadence and Mentor Graphics and others, it may also be considered a physical instantiation.
The MIPS Approach to IP Platforms
The MIPS® platform architecture is implemented with MIPS Technologies and partner intellectual property (IP), with all platform usages fully tested and validated under the company’s new MIPS-Verified™ program. MIPS Technologies will leverage its extensive ecosystem, including software tool and RTOS vendors, and IP and Electronic System-Level (ESL) companies to ensure full software support for the new SOC-it® Platform.
MIPS Technologies is defining the basic hardware platform as well as a Hardware Abstraction Layer (HAL). This allows the underlying hardware to be changed without affecting software compatibility. The HAL is also extensible to support partner supplied devices.
There are two main elements of the hardware platform:
Figure 5: MIPS IP Platform
An additional component is the SOC-it® L2 Cache Controller, designed to minimize memory latency, reducing system costs and power consumption. Fully synthesizable, the SOC-it L2 Cache Controller works seamlessly with all MIPS Technologies OCP-based cores and uses standard cell libraries and memory arrays.
As described earlier, the platform will be available as synthesizable RTL, but also as SystemC models at various levels of abstraction, suitable for SoC designers and software development teams. These models will be compatible with the common ESL tools available on the market today.
Finally, MIPS Technologies will work with the leading embedded software companies to ensure that software support in development tools and RTOS/OS software platforms is available. These key companies include Express Logic, Mentor Graphics, MontaVista and Wind River. Users of the platform can then leverage this enablement.
The MIPS Technologies platform strategy is based on current Electronic System Level (ESL) design and platform-based design trends. It describes a framework for a MIPS-Based IP Platform that comprises re-usable, software and hardware supported sub-systems that customers can utilize in their SoC designs. By standardizing on this framework and by engaging with ESL and IP vendors, SoC and system designers can leverage the investments made in our own products and with third parties.
The approach is different from approaches taken by other IP companies, in that MIPS Technologies looks to the MIPS Ecosystem to supply best-in-class components of the hardware/software platform. This provides the customer with competitive choice in obtaining the IP components.
MIPS Technologies, Inc.
Mountain View, California USA
Abstract:
Sustaining high processor performance in real-world applications requires careful SoC architecture. For example, an L2 cache may be needed to minimize memory latency, especially for single-threaded processors; additionally, a high-performance non-blocking interconnect fabric is often essential to avoid data transfer bottlenecks.
With time-to-market pressures mounting for complex 90nm and 65nm SoCs, MIPS Technologies and its partners can now offer fully verified platform architectures and supporting environments. This presentation will provide insight into a new high-performance platform architecture for MIPS-Based™ SoCs. A key goal is to allow high peak processor performance to be sustained for real-world applications which – unlike Dhrystone– include cache miss, interlock stalls and interrupts.
The platform architecture will be implemented with both new MIPS designs as well as partner IP with all platform implementations fully verified by MIPS Technologies. The architecture allows MIPS processors to sustain high performance under realistic workloads. MIPS customers will also benefit with improved time-to-market. The platform architecture provides numerous configuration options to support the wide variety of SoC requirements.
This presentation will also outline the ESL tools required to support performance analysis for proper selection among the numerous platform configurations as well as software debug.
Why use Platforms?
The concept of platform-based design for SoC and embedded systems is rapidly gaining traction among platform vendors and users.
Vendors appreciate the following advantages:
- A platform provides the means to package or bundle previously separate offerings and maximize the return or value of those offering. This is supports the principle that ‘the whole is greater than the sum of its parts’
- The vendor’s revenue from a market segment increases by going beyond a core product offering
- With an industry-standard platform, the vendor gains advantage by controlling the platform definition
- A platform can be a barrier to entry for competitors
- A platform represents a basis for working with third parties who will support the platform and increase its value
- A platform can provide real time-to-market, reduction of risk and cost advantages by the use of a pre-defined, pre-verified set of components.
- By choosing a platform that has industry support, a user can rely on third parties to meet needs not supplied by the supplier of the platform.
- A user can achieve time-to-market improvements and cost reductions by re-using the platform for incremental product releases or re-targeting the platform for other applications, including sharing across divisions within the same company.
- The user of a platform can focus resources on further developing core competencies or increasing differentiation from competitors.
- A particular platform may allow a user to compete in a chosen market segment that he otherwise could not compete in.
In embedded systems, there are SoC Platforms produced by the semiconductor vendors, IP Platforms offered by IP vendors and Software Platforms from vendors in the embedded software market.
SoC Platforms
In the SoC world, most platform discussion revolves around using SoC platforms as a methodology to design a family of semiconductor products. The SoC platform chip is a product that results from using a platform-based methodology.
Figure 1 A MIPS-Based™ Digital Video Platform
Figure 1 shows a Digital Video Platform from Philips based on the Nexperia Platform. Beyond the MIPS core, additional functionality is required for the application. Some of this is common industry-standard I/O and other peripherals, but much application-specific IP is required as well. In addition, the vendor provides a great deal of functionality in the form of software, supplying or enabling the software development tools to use with the platform. The SoC is only part of what the vendor must offer the OEM customer. Normally, they must provide a reference design based on the SoC.
Figure 2 TI's OMAP ARM-based platform
Figure 2 shows TI’s OMAP platform. Like the Nexperia platform, this is a dual processor system and, again, TI has had to add considerable additional IP beyond the licensed ARM core.
As well as the main SoC chip, there is usually much other functionality supplied in support chips from the platform vendors and other suppliers.
IP Platforms
In contrast to the SoC platforms developed by semiconductor vendors, IP platforms tend to be much less comprehensive and are usually market-specific as opposed to application-specific.
The ARM PrimeXsys platform, originally developed as a wireless platform, is an extension of their business of supplying IP components for use with the ARM processor core.
Figure 3 An IP Platform
Software Platforms
While not the primary topic of this paper, software platforms play an important role in the design of embedded systems. This type of platforms usually consists of an RTOS or OS, middleware, application specific software and the development tools for use with the platform.
Figure 4 Wind River's Consumer Devices Platform
An example of this type of platform is shown in Figure 4. This is a software platform that is not application-specific, but has the common functions used in the design of consumer devices.
Requirements for an IP Platform
The IP components for a platform (and for SoC Design, in general) must be available in forms that allow its integration into an SoC design flow. This means supporting the common EDA design flows and modeling the IP at different levels of abstraction.
Synthesizable IP Platform
An IP Platform must have components that are available as RTL. A synthesizable platform is the combination, in RTL Verilog, of the semiconductor IP components. The platform must be configurable to allow the user to add, modify and delete components. The RTL must also contain the necessary support and scripts to be synthesizable using commercially available tools. A configurable test bench that allows the user to run verification tests on his particular configuration is also part of the platform. This level of abstraction is what a semiconductor or SoC vendor ultimately would develop or license from an IP company, to perform his SoC design.
There are platform building tools for this type of platform available from companies such as Mentor Graphics and Synopsys.
The SPIRIT consortium has defined a format for describing the components and these tools allow platforms to be built from components that are specified using the SPIRIT format.
System-Level/Virtual Platform Modeling
A system level model is a functionally accurate and/or timing accurate component that models the behavior, timing and interfaces of some or all of the components of the platform and provides control and visibility of the internal state of the hardware. These models provide cycle and timing accuracy or timing-close accuracy and are written in System C, C/C++ or a derivation thereof, and these will then run much faster than the source RTL or gate-level simulation. The modeling of the system may use transaction-based modeling to describe the interaction of components with a staged progression to more and more accuracy. The Open SystemC Initiative (OSCI) has defined transaction level modeling specifications for SystemC models.
At a higher level of abstraction, this type of modeling commonly involves virtual platforms. They are configurable or fixed simulation platforms that can run with real operating system images and real application software. Each virtual platform is an executable representation of the components of a SoC platform. It runs on a host workstation under the control of an application on the host machine. The modeling concentrates on the functionality or behavior of the system and sacrifices timing accuracy for performance. This approach allows operating systems to boot and run with reasonable response times. It allows applications, device drivers and sometimes OS ports to be developed. The models are normally written in C/C++, System C or some language designed especially for this purpose.
In addition to emulating the ‘internal’ components of the system, a virtual platform also emulates the external devices connected to the peripheral interfaces. This can include memory, hard disks, terminals, switches, LEDs, keyboard, mouse and displays. In some cases, the Virtual Platform may connect virtual components to real components on the host system. For example, the keyboard input comes from the host’s real keyboard.
Tools for system-level/virtual platform modeling
are available from the major EDA and ESL vendors including CoWare, Mentor Graphics, Summit Design, Synopsys and VaST.
Physical Platforms
Physical platforms normally take the form of a development board containing the components in a chip or an FPGA. Real devices such as keyboards, displays, hard disks, etc., connect to provide a single board computer running an operating system or monitor. A prototyping area, normally utilizing FPGAs, is available for expansion of the platform. In addition, external I/O buses, such as PCI-Express, make the platform expandable for vertical applications or debug use. If the design is transferred to an emulation system from vendors such as Cadence and Mentor Graphics and others, it may also be considered a physical instantiation.
The MIPS Approach to IP Platforms
The MIPS® platform architecture is implemented with MIPS Technologies and partner intellectual property (IP), with all platform usages fully tested and validated under the company’s new MIPS-Verified™ program. MIPS Technologies will leverage its extensive ecosystem, including software tool and RTOS vendors, and IP and Electronic System-Level (ESL) companies to ensure full software support for the new SOC-it® Platform.
MIPS Technologies is defining the basic hardware platform as well as a Hardware Abstraction Layer (HAL). This allows the underlying hardware to be changed without affecting software compatibility. The HAL is also extensible to support partner supplied devices.
There are two main elements of the hardware platform:
- The first part is a hardware kernel of components, available directly from MIPS Technologies. This consists of functionality critical to maximizing system performance, including the memory sub-system, interrupts and on-chip interconnects.
- The second element consists of the common peripherals required in most embedded systems today, including Real Time Clock (RTC), Serial Port (UART) and General Purpose I/O (GPIO). Customers may choose the source of the common peripheral IP, but still retain software compatibility by use of the HAL.
Figure 5: MIPS IP Platform
An additional component is the SOC-it® L2 Cache Controller, designed to minimize memory latency, reducing system costs and power consumption. Fully synthesizable, the SOC-it L2 Cache Controller works seamlessly with all MIPS Technologies OCP-based cores and uses standard cell libraries and memory arrays.
As described earlier, the platform will be available as synthesizable RTL, but also as SystemC models at various levels of abstraction, suitable for SoC designers and software development teams. These models will be compatible with the common ESL tools available on the market today.
Finally, MIPS Technologies will work with the leading embedded software companies to ensure that software support in development tools and RTOS/OS software platforms is available. These key companies include Express Logic, Mentor Graphics, MontaVista and Wind River. Users of the platform can then leverage this enablement.
The MIPS Technologies platform strategy is based on current Electronic System Level (ESL) design and platform-based design trends. It describes a framework for a MIPS-Based IP Platform that comprises re-usable, software and hardware supported sub-systems that customers can utilize in their SoC designs. By standardizing on this framework and by engaging with ESL and IP vendors, SoC and system designers can leverage the investments made in our own products and with third parties.
The approach is different from approaches taken by other IP companies, in that MIPS Technologies looks to the MIPS Ecosystem to supply best-in-class components of the hardware/software platform. This provides the customer with competitive choice in obtaining the IP components.
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