Deploying Mixed Signal IP -- Is ''No Re-Spin'' Just Spin ?

By Brendan Farley, Silicon & Software Systems (S3) Dublin Ireland

Abstract:

The traditional wisdom in mixed mode System on Chip (SOC) design is that at least one re-spin should be planned. This is due to the risks involved in instantiating sensitive mixed signal circuits onto less than ideal manufacturing processes in the presence of significant digital interference.

One of the key benefits for the customer in the growth of the IP market has been the increasing availability of silicon proven high performance data converters, typically the bottleneck in overall system performance. So has the mixed signal IP business removed the need for the traditional mixed mode SOC re-spin?

In this paper, the residual technical challenges and risks associated with deploying high performance mixed signal IP on SOCs is explored. The integration challenges facing both the IP vendor and customer are analyzed and a risk mitigation strategy is proposed.

1 Mixed Signal IP Concept

According to Dataquest’s most recent IP market report [1], the mixed signal data converter IP market grew by 60% from 2004 to 2005. New applications areas such 802.11n, WiFi and TV on mobile are driving much of this growth.

There are strong reasons why certain types of mixed signal components should conform to the IP-only business model. The primary reasons include risk and lead time mitigation. However, in reality, it can be challenging for vendors to easily shrink-wrap the IP component, the customization needed and the required customer support into one bundle. Vendors continue to balance these and other factors to determine which mixed signal architectures lend themselves to the straightforward IP model. Such an IP model envisages multiple licensing of the same component without circuit modification.

Figure 1 shows a typical wireless analog front-end (AFE) implemented by S3 at 90nm / 65nm CMOS for multiple customers. S3’s wireless AFEs are integrated into large SOCs with millions of digital gates. The AFE includes an array of component types that have been shown to conform well to an IP model and include ADC, DAC and PLL. Circuits which do not fit well the IP model include filters and amplifiers where there is a wide range of implementation specific design variables

Figure 1: Example Wireless Analog Front-end

2 Typical Data Converter IP Engagement

In the mixed signal SOC design business the IP is silicon proven and characterized by the vendor in advance. The vendor delivers characterization reports, test silicon samples and customer demonstration board to the customer to prove the advertised performance of the IP as part of the presales activity.

However, the risk introduced in mapping this IP onto customer silicon can be significant. This is especially true in the high performance data converter part of the mixed signal IP market. One can envisage the journey which the core mixed signal data converter takes as it progresses toward customer silicon. This journey can result in a significantly transformed IP end-silicon instantiation and a new SOC operating environment.

The customer specific requirements are captured as part of the commercial agreement and the data converters re-targeted to the customer’s preferred implementation.

Changes to the IP and its silicon proven environment can include:

• application specific customization (e.g. power optimization for a given sample rate)

• customer modifications for product differentiation and electrical interface interoperability

• modifications related to customer’s use of available process flavors(e.g. low power, generic, high performance) and transistor devices within each technology flavor (e.g. standard/low/high TV to trade-off transistor performance and mask / wafer costs)

• circuit interfaces to the IP including analog preprocessing circuitry and output loading circuitry

• IC floor plan and pad-ring configuration

• IC complexity including number of gates and die size

• level and nature of on-chip disturbance including clock speeds and on-chip decoupling

• package and supply / signal bonding

Figure 2: Typical IP Transformations

In summary, the mixed signal IP will find itself in a modified form and a very different SOC environment whence it was first silicon proven. This factor can fundamentally affect its performance and add risk to the customer’s overall product development.

3 Risks in Data Converter IP Deployment

By requesting application specific modifications to the IP, customers introduce additional risks into the product development. Indeed, deploying silicon proven mixed signal IP into an SOC environment which is new will always carry risk

At the circuit design level, transistor level simulation models are becoming more accurate within a well defined environment. However, as process scaling extends to 90nm and 65nm, the transistors performance is increasingly affected by its physical environment and its proximity to other devices. Such effects are not adequately captured by the extraction and simulation tools and so the measured silicon results may be significantly different to those achieved by simulation. So simulation of modifications to silicon proven IP may not sufficiently de-risk the design.

At the top-level, each time the IP macro is deployed in a new SOC, new effects may be observed from the changed environment. For example, the IP may have interoperability problems with new interfacing blocks supplied by the customer or other vendors. Typical interoperability problems encountered in AFE integration include:

• Crosstalk (e.g. through the pad-ring)

• Digital interference through the common substrate

• Interference through common supplies.

• Supply domain crossing interference. e.g., PLL clock entering ADC supply domain

• Mismatch between the source and termination impedance of connected IP components e.g. kickback from the ADC onto the amplifier or filter that is driving it

In the event that such problems are encountered in silicon, it can be difficult to identify the source of the problem. Even though each IP block will work well in isolation, the problem will only manifest itself during application mode. The IP vendor will be keen to demonstrate that the IP block is performing in isolation as per specification in order to close out the contract. However, limitations in the interoperability of the IP component may severely restrict the overall SOC performance.

4 Mixed Signal IP Testing

It is important that the vendor and customer agree a plan at the contractual stage for final acceptance of delivered IP blocks. This plan should include mutually agreed acceptance criteria and a means of demonstrating that these criteria have been met. Generally, the customer will provide an application board for IP acceptance testing.

The application board can be dual purpose – IP acceptance testing and various customer applications. This board may work well for the application but for IP acceptance, monitoring of normally isolated signals may affect the measured performance of individual IP blocks. A customer sourcing the analog IP will require detailed guidelines from the vendor regarding the sensitivities of the IP blocks to board design issues. The vendor needs to work closely with the customer, possibly reviewing board schematics and layout with respect to acceptance test features.

5 Deploying Data Converter IP

In most cases, the performance of the mixed signal data converter IP is central to the overall performance of the SOC. However, the risk in embedding the data converter in a complex SOC can be high and dependent on the top-level IC implementation.

At S3 we have integrated our mixed signal IP components into many high performance customer IC’s targeting markets such as WiFi, WiMax, TV Tuner, TV-on-Mobile and HDTV at technologies up and including 90nm. Each IC integration project does vary but the overall deployment strategy remains consistent.

If the core data converter implementation has been modified / customized for the specific customer deployment for reasons already discussed, a dedicated test chip should be considered as part of a risk mitigation strategy. In S3’s experience, major modifications to the IP requiring a test chip would include a foundry change or re-targeting to a different process option. Performance optimization has lower risk but needs to be considered on a case by case basis.

S3 recommend the placement of Deep Nwell beneath the mixed signal IP for isolation purposes. This should be connected to a quiet supply which will prevent residual substrate noise from coupling to the analog circuitry. Deep Nwell should also be placed under all digital logic and connected to a separate supply to prevent digital noise contamination of the substrate. If possible, the i/o components in the padring should also be isolated from the substrate using Deep Nwell for similar reasons. This strategy may require close cooperation with the standard cell, memory and I/O library vendors.

The mixed signal IP components should be a central consideration for the floorplanning task of the SOC design. The mixed signal circuitry should be placed as close as possible to the analog input, output and supply bondpads. The ‘quiet’ digital blocks, such as memories, should be placed between the analog blocks and the noisy digital blocks in order to maximize the distance through the substrate of noise coupling components.

The padring design is of critical importance in mixed mode SOC design. Digital and analog I/O supply domains should be partitioned and isolated from each other while remaining consistent with a robust esd strategy. Any integrated oscillator embedded in the padring should have a dedicated power supply when providing a reference clock for dataconverters or PLLs. Output buffer slews should be selected for minimum on-chip disturbance. Sensitive analog input and output pads should be placed centrally in the padring to minimize bond wire lengths and away from noisy pads. Each analog input / output differential pad pair can be separated from noisier I/O signals by placing static or quiet bondpads on either side.

From past experience, we know that interoperability presents a major risk with the IP model. Data converter interfacing circuits such as amplifiers and filters should be designed and co-simulated with a great deal of transparency to ensure system level performance is achieved. The mixed signal IP blocks should be co-simulated with interfacing circuitry at the transistor level, to detect transient interoperability effects such as kick-back from sampling circuitry or supply ripple on regulator outputs. Mixed signal system performance often falls down as a result of sensitivities in the interfacing and interoperability of blocks rather than the individual performance of the blocks themselves.

Drawing peak current directly through inductive bond wires will generate high frequency supply noise. Therefore, use of local on-chip linear regulators for both digital and analog sections of the SOC is desirable. Local regulators will allow greater availability of isolated supply domains without the requirement of additional pin count. The digital blocks should be adequately decoupled locally and the use of damping series resistance in the supply path should be considered but traded with supply drop.

Package and bond wire parasitics for each deployment should be included in co-simulations of the IP to verify its expected performance.

Design for test is a key enabler for the IP business model, allowing the vendor to demonstrate the IP performance inside the customer application. Test modes should be available to allow direct access to each delivered IP blocks in isolation to allow access to combinations of IP blocks (analog test bus, buffers). Performance should also be measurable with all other blocks active. This mixed signal IP test strategy should be complimentary to the production test strategy of the SOC.

Implementation of these techniques will reduce risk and every effort should be made to quantify this improvement in advance. A simulation model of the SOC environment including supply network, package and pin parasitics, substrate coupling, interfacing circuitry, padring and digital circuitry can be developed and used to analyze the sensitivities of the mixed signal IP inside the system.

To adequately address all of these deployment issues, the IP vendor clearly needs to be intimately involved in the SOC integration process. At S3 we have found that customers engaging in mixed signal IP licensing prefer to pass the SOC integration responsibility to the mixed signal IP vendor as part of a risk mitigation strategy. The tasks can include digital back-end implementation; custom mixed signal design, pad-ring construction and chip integration in conjunction with the mixed signal IP delivery.

The vendor can work with the customer in I/O planning, IC floorplanning and integration of the memories, digital components, analog blocks and I/O pads in a way which maximizes mixed signal IP performance. By taking the most sensitive components (i.e. the mixed signal IP) and physically implementing the rest of the system around these components, a more optimum system implementation can be achieved in terms of risk and performance - thus avoiding a costly re-spin.

6 Conclusion

The mixed signal data converter IP market is growing strongly, reflecting an on-going market trend toward full SOC integration. However, accessing reduced cost through mixed signal integration can result in increased risk due to the sensitivities of the IP components when integrated into an SOC. The silicon proven model does help in this regard but customer specific customization of the IP and embedding in a new SOC environment creates significant risk. By working with the IP vendor closely and leveraging the vendor’s deployment knowledge and capability, this residual risk can be addressed and avoid the requirement for a costly re-spin.

7 References

[1] Market Share: Semiconductor Intellectual Property, Worldwide, 2005 Gartner Inc. (May 2006)