By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies Apr 18 2007 (0:15 AM), Embedded Systems Design
System-on-chip (SoC) designers know what it's like to do more with less. They're constantly challenged by ever-increasing constraints on system cost and power consumption while being tasked with increasing the performance and functionality of their designs. The tricks of the trade available to designers are, at best, a set of difficult trade-offs.
For example, some designers ramp up the processor's clock speed, but this approach usually results in higher power consumption. In addition, memory performance hasn't kept pace with processor technology, as Figure 1 illustrates, and this mismatch limits any significant gains in system performance. A multicore system is another option, but this suffers from a larger die area and higher cost. Any performance increase comes at a fairly substantial cost in silicon and system power.
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