By Dean Wiltshire, Mentor Graphics Corporation, Courtesy of EDA DesignLine
Apr 19 2007 (8:12 AM)
This article discusses the disconnect between the digital design engineer's vision of bus structures on the printed circuit board (PCB) and the failure of tools to capture and route this vision in an efficient manner. Around the globe, there are many different electronic system design flows and roles. This article assumes a design flow that may or may not match the flow and roles of your organization, yet the solutions discussed fit into any flow. The first part of this two-part article follows the capture of Intellectual Property (IP), by the design engineer and collaboration of this IP throughout the remaining design flow. The second part of this article focuses on the PCB designer collaboration of the IP through the remaining design flow.
While designing and capturing the logic, the design engineer has envisioned the bus structure and its relationship among the components. This envisioned structure is considered IP, typically a valuable asset to their organization. The problem is capturing and sharing this IP.
Often, design engineers attempt to capture and communicate IP in a hand drawn document or on a paper napkin. While many aspects of EDA are in fact automated, this process has not had effective tool support. A hand drawing on a napkin has been the most efficient to date.
While quick to capture, the napkin may or may not physically map to the PCB. This is a problem because of size issues, such as width of the physical bus, mechanical parameters of the card, physical size and pin outs of components. Therefore, the original IP may be completely invalid because it is physically impossible to follow; EDA tools must not only replace, but also improve upon the napkin. They must effectively capture the IP and communicate accurate, usable/reusable IP throughout the design process.
When the IP is accurately captured, collaboration is required throughout the remaining design flow. Effective collaboration shortens the design timeframe by preventing the re-entry of IP by others. Additionally, by using the exact IP, the original intent is maintained. Errors and misunderstandings are removed with effective collaboration with the results being increased efficiency in the design flow.
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