By Davin Lim, XilinxApril 25, 2007 -- pldesignline.com
What is the biggest factor affecting the productivity of FPGA design cycles? Many designers say achieving timing closure is critical in getting a design to market – and with good reason. Achieving timing closure in an efficient manner with confident results is what every designer seeks, yet this is only one part of the picture. To be truly efficient within the whole design cycle, designers depend on the overall design environment and the tools within them to manage process complexity and provide real solutions for their particular style and approach to FPGA design. A complete, effective design environment provides focus and transparency. Like many good tools, the best offer a seamless solution.
Some of the main features a complete FPGA design environment should include for maximum productivity are as follows:
- Quickly identify timing issues – Tools must give designers immediate access to critical information to see potential timing bottlenecks.
- Explore results using a range of views – Not all problems are solved in the same way. Good tools allow designers to look at timing paths from multiple perspectives. They always give enough detail but also keep things focused.
- See the design, not the tool – This means seamless switching between views so that the tool operation is transparent, but the design issues are clear.
- Get meaningful, intermediate results – Productivity includes being able to monitor design performance at earlier stages. If a designer can resolve issues earlier, this directly leads to more turns per day.
- Manage complex source code structures – FPGA design tools need to facilitate the management of source files with means to provide compatibility with a designer's preferred source code control mechanisms.
The following examples address the above topics in detail using a design tool that supports faster and easier timing closure and stays focused on the design.
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