English
Analog and Mixed-Signal Connectivity IP at 65nm and below
By Navraj S. Nandra, Synopsys, Inc.
The demand for connectivity intellectual property (IP) for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as these standard interfaces are included in SoCs designed for applications such as single chip recordable DVD CODEC's and MP3 players. In order to stretch battery life of these SoCs, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes that enable production of very low-power SoCs for these mobile platforms and small form-factor devices. Today, many of these SoCs are manufactured in 90nm process nodes, and the ramp for 65nm design starts has been more aggressive than expected. The 45nm process design is following close behind, with early versions of design rules and process parameters already available.
The challenge from the IP provider's viewpoint is to meet analog performance in a technology that has been targeted for densely packed digital logic. From the SoC integrator's perspective, the IP should be easy to integrate. The IP provider should have already dealt all of the details of creating the IP. The IP should also incorporate new circuit design techniques that accommodate lower supply voltages necessary for portable systems. At the smaller process nodes, design for manufacturing (DFM) must also be taken into account.
Creating IP at 65nm and Below
Reduced supply voltages mean that architectures that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without any loss in performance. One way to address this is to use a mixture of high voltage I/O devices with the lower voltage core devices. This will be discussed in the next section. In addition, all the post processing to support DFM requirements increases the performance variation in these devices. This is due to effects like shallow-trench isolation (STI) induced stress, (NMOS becomes slower and the PMOS faster) nwell proximity effects, contact stress and phase shift mask correction algorithms. There is also a time-dependent variation due to negative bias temperature instability (NBTI) in PMOS devices and hot carrier injection (HCI) in NMOS devices.
The demand for connectivity intellectual property (IP) for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as these standard interfaces are included in SoCs designed for applications such as single chip recordable DVD CODEC's and MP3 players. In order to stretch battery life of these SoCs, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes that enable production of very low-power SoCs for these mobile platforms and small form-factor devices. Today, many of these SoCs are manufactured in 90nm process nodes, and the ramp for 65nm design starts has been more aggressive than expected. The 45nm process design is following close behind, with early versions of design rules and process parameters already available.
The challenge from the IP provider's viewpoint is to meet analog performance in a technology that has been targeted for densely packed digital logic. From the SoC integrator's perspective, the IP should be easy to integrate. The IP provider should have already dealt all of the details of creating the IP. The IP should also incorporate new circuit design techniques that accommodate lower supply voltages necessary for portable systems. At the smaller process nodes, design for manufacturing (DFM) must also be taken into account.
Creating IP at 65nm and Below
Reduced supply voltages mean that architectures that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without any loss in performance. One way to address this is to use a mixture of high voltage I/O devices with the lower voltage core devices. This will be discussed in the next section. In addition, all the post processing to support DFM requirements increases the performance variation in these devices. This is due to effects like shallow-trench isolation (STI) induced stress, (NMOS becomes slower and the PMOS faster) nwell proximity effects, contact stress and phase shift mask correction algorithms. There is also a time-dependent variation due to negative bias temperature instability (NBTI) in PMOS devices and hot carrier injection (HCI) in NMOS devices.
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