By Deepak Shankar, Mirabilis DesignMay 14, 2007 -- dspdesignline.com
DSP systems often include multiple embedded processors and hardware accelerators. The performance of these systems is typically limited by factors such as I/O bandwidth, memory distribution, and memory speed. This is particularly true when the system components share a memory interface. For such systems, it is critical to choose the right memory controller.
Different memory controllers offer latency distributions that make them suitable for specific applications. For example, a slot-based controller with fixed priorities can offer deterministic latencies, while buses such as PCI-Express and CoreConnect offer lower latency at peak loading but higher average latency.
It is extremely difficult to predict the performance of the memory system and the effect of contention without a solid model of the system. It is therefore important to invest in modeling before beginning development. This modeling should include allocating of threads/tasks to resources, identifying any custom hardware needs, and determining the size and speed of the I/O. The modeling can performed using a number of methods, including "back of the napkin" calculations, spreadsheet analysis, or by building a physical prototype.
In this article, we examine a unique "virtual prototyping" approach to modeling. We use this approach to model a MPEG II application in a Xilinx FPGA. We evaluate two memory access schemes for this application: the MPMC Memory Controller from Xilinx, and the CoreConnect Bus specification for FPGAs.
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