By Rick Eads, Agilent TechnologiesMay 21 2007 (12:00 PM), Courtesy of Embedded Systems Design
What do you need to know about physical-layer compliance measurements under the PCI Express 1.1 specification? Significant changes in jitter and phase-locked loop (PLL) bandwidth were instituted with this revision of the PCI Express 1.0a specifications. Yet, perhaps the most important point to remember is that the PCI-SIG (the governing body of PCI Express) will soon require enforcement of the PCI Express 1.1 standard for vendors who wish to have their products listed on the PCI-SIG's PCI Express Integrators List.
PCI Express (PCIe) is the next-generation evolution of the PCI interface bus that's the dominant I/O interconnect found in today's desktop, server, and mobile computing platforms. The bus currently operates at 2.5 Gbits/s across up to 16 lanes, providing a maximum transfer rate of 40 Gbits/s. While deployment of PCIe 2.0 (at 5 Gbits/s) is just beginning, the majority of today's add-in card and motherboards deploy various flavors of PCIe interfaces operating at the 2.5-Gbits/s rate.
Wide implementation of PCIe didn't happen by accident. The authors of the specification and the PCI-SIG board of directors worked hard to ensure that products bearing the PCIe logo met a consistent level of performance and quality. The reason for this is simple—when you buy a PCIe product from one vendor you expect it to work without reservation with other products as its designers intended. This consistent and reliable interoperability is key to adoption of any standard interface.
As a designer who intends to use PCIe in your product, one of your key responsibilities is to respect the PCI standard and work to ensure that design complies to its electrical and transactional requirements. Interoperability starts at the physical layer with well-designed transmitters, receivers, transmission lines, and interconnects.
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