Analog behavioral models reduce mixed-signal LSI verification time
Jun 22, 2007 (12:52 PM) -- Planet Analog
Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for full-chip verification is still taking a long time (Figure 1a and Figure 1b).
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Current methodologies are no longer sufficient or acceptable, so new verification methods are needed.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Mixed-signal SOC verification using analog behavioral models
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-Signal Verification for USB 2.0 Physical Layer IP
- Analog and Mixed-Signal Connectivity IP at 65nm and below
- Improve performance and reduce power consumption in mixed-signal designs
New Articles
- Rising respins and need for re-evaluation of chip design strategies
- Simplifying analog and mixed-signal design integration
- AI-driven SRAM demand needs integrated repair and security
- Understanding the contenders for the Flash memory crown
- Select the Right Microcontroller IP for Your High-Integrity SoCs
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- UVM RAL Model: Usage and Application