English
Commentary: SystemVerilog enables design with verification
Michal Siwinski, Cadence Design Systems
(06/26/2007 12:35 PM EDT)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts from proven verification languages, property/assertion languages, and even object-oriented programming languages. With its many new features, SystemVerilog can appear a bit daunting in its entirety.
Partly for that reason, and partly because of the history of the donations that influenced the standard, it is common to divide the new features of SystemVerilog into three categories: assertion constructs, design constructs and verification constructs. This categorization has some merit, at least from a syntax perspective, but it can be misleading, in that logic designers use more than the design constructs, and verification engineers use more than the verification constructs.
(06/26/2007 12:35 PM EDT)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts from proven verification languages, property/assertion languages, and even object-oriented programming languages. With its many new features, SystemVerilog can appear a bit daunting in its entirety.
Partly for that reason, and partly because of the history of the donations that influenced the standard, it is common to divide the new features of SystemVerilog into three categories: assertion constructs, design constructs and verification constructs. This categorization has some merit, at least from a syntax perspective, but it can be misleading, in that logic designers use more than the design constructs, and verification engineers use more than the verification constructs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Design patterns in SystemVerilog OOP for UVM verification
- Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim
- System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study
- Transactions in an OVM SystemVerilog Verification Environment
- Development of Verification Environment for Layered Protocol using SystemVerilog