By Dean Wiltshire, Mentor Graphics CorporationJuly 30, 2007 -- edadesignline.com
This article is the second part of the two part article covering Topology Planning and Topology Routing. The first part covered a Design Engineer capturing Intellectual Property (IP) for a unique circuit and collaboration of this IP through the remaining design flow of a PCB. This second part focuses on the PCB designer collaboration of the IP and further employing Topology Planning and Topology Routing tools to support the IP and complete the PCB design. Part one can be found at:Capturing and Sharing Intellectual Property in PCB DesignTopology Work Flow
In Figure 1, we see the role of the design engineer capturing IP by placing the few necessary components and planning critical interconnect flow between these components. Once captured this information is seamlessly provided to the PCB designer where they can complete the remaining design.
1. Flow of PCB design with design engineer capturing IP and seamless integration with PCB designer to finish design.Click here for a larger version
Rather than going through the interactive and iterative process between engineer and designer to capture the correct intent, the design engineer has captured this information and done so accurately making it useful to the PCB designer.
For so many designs, the engineer and designer go through an interactive placement and routing, consuming both professional's valuable time. Historically, it is a necessary interaction, yet with time consuming inefficiencies. The original plan provided by the engineer may have been a hand sketch without appropriate scales of components, bus widths or pin outs.
As the designer engages with the design, placement of certain components and interconnect are captured by the engineer using topology planning techniques. Yet, the design is not complete with other components to place and probably other IO and bus structures to capture and all interconnects complete.
Like the design engineer, the PCB designer employs topology planning while interacting with both placed and unplaced components. Working this scenario produces the optimum placement and interconnect plan " providing density efficiencies.
As critical and dense areas are placed and topology plans captured, placement may be completed prior to the finished topology plan. Therefore, some topology paths may have to work with existing placement " they're a lower priority, yet still need to be connected.
Click here to read more ...