32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Analysis: Tensilica's D1 Video Engine
Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it's one of four new dual-core "VDO" video engines from Tensilica. The 388VDO is the highest-performance member of the quartet and supports a variety of video codec standards at resolutions up to D1 (i.e., standard definition television). Target applications include chips for mobile handsets and personal media players.
The 388VDO incorporates two heterogeneous processor cores, each of which is configured to support different types of processing. One core supports 16- and 8-way SIMD operations and is optimized for the highly data-parallel processing that's characteristic of tasks like motion compensation and transforms; this core is called the "pixel processor." The other is optimized for the sequential processing needed for decision-making and bitstream unpacking; this core is called the "stream processor."
E-mail This Article | Printer-Friendly Page |
Related Articles
New Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Maximizing ESD protection for automotive Ethernet applications