Implementing an FPGA-based scalable OFDMA engine for WiMAX
(08/21/2007 10:45 AM EDT) -- EE Times
Scalable orthogonal frequency-division multiple access (OFDMA) is a key physical layer component associated with mobile WiMAX. It is an enabling technology for future broadband wireless protocols including 3GPP and 3GPP2 and their long-term evolution.
The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks.
Symbol mapping and demapping are used in bit-level processing, as well as forward error correction (FEC) based on Reed-Solomon and Viterbi MegaCore functions. FEC schemes such as convolution turbo codes from third-party vendors can be used as well. OFDMA symbol-level processing includes subchannelization and de-subchannelization.
Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) MegaCore functions support cyclic prefix insertion. Digital IF processing includes single- and multiple-antenna digital up converters (DUCs), digital down converters (DDCs), advanced crest factor reduction (CFR), and digital pre-distortion (DPD). The IF modem package allows easy and efficient multi-channel and time-multiplexed implementations.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Intel FPGA Hot IP
Related Articles
- How to design a scalable OFDMA engine for WiMAX
- Tap into the advantages of a scalable OFDMA engine for WiMAX
- FPGAs: Embedded Apps : FPGA-based FFT engine handles four times more input data
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
- Designing a high-definition FPGA-based graphics controller
New Articles
- Rising respins and need for re-evaluation of chip design strategies
- Simplifying analog and mixed-signal design integration
- AI-driven SRAM demand needs integrated repair and security
- Understanding the contenders for the Flash memory crown
- Select the Right Microcontroller IP for Your High-Integrity SoCs
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- UVM RAL Model: Usage and Application