Amjad Qureshi, Cadence Design Systems(08/27/2007 8:57 AM EDT) -- EE Times
As system-on chip (SoC) designs become more complex, verification remains the critical challenge. Larger teams continually use more resources to search for the most efficient ways to integrate new methodologies and ultimately design with verification in mind. Although we know that implementing a verification plan accounts for nearly two- thirds of the overall chip design effort, we continue to see teams delivering chips late and missing projected tape-out deadlines. This type of carelessness can result in serious consequences to the business, because it means that hardware and software bugs often escape discovery until late in the design cycle.
To create a comprehensive verification solution, we must first acknowledge both the differences and the challenges that designers and verification engineers face. In the process, we find that certain gaps are inadvertently neglected. The first major gap that is commonly overlooked is "reuse." Often, block-level verification environments are not leveraged within the cluster level (subsystem) or the chip level, which presents a major problem.
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