By Chin-Yao Chang and Kuen-Jong Lee, National Cheng Kung University, Taiwan, Alan P. Su, SprintSoft, Inc, Taiwan, Mark Burton, GreenSocs, UK
September 04, 2007 -- edadesignline.com
As the VLSI process technology continuously advances, the System-on-Chip (SoC) design methodology has become a main design trend for semiconductor products. A single SoC containing multi-million gates for audio/video/communication applications is now a commonplace in electronic industry.
However, challenges arise due to the high complexity of SoC design . For example, the simulation time to verify an SoC is often too long to meet the time-to-market requirement. In general the simulation speed relates to the abstraction level of the SoC description. Although Verilog and VHDL, the two main hardware description languages employed today, support abstraction levels up to the functional level, the nature of Verilog and VHDL restricts them from achieving high simulation speed. Also the lack of high-level programming language features such as inheritance, reference, thread, and dynamic resolution makes it hard to use Verilog and VHDL to develop high-level models and systems.
In recent years the Electronic System Level (ESL) design methodology has been proposed to solve SoC design problems. SystemC, the main ESL hardware description language, is C++ based with hardware constructs such as modules, ports and clocks. SystemC allows users to model components and systems at higher abstraction levels than Verilog and VHDL. One key feature of SystemC is the Transaction Level Modeling (TLM)  that models components and systems at a level higher than the functional level in the sense that the data passing is modeled as transactions instead of signals. By raising the abstraction level we can perform: (1) algorithm/architecture codesign, (2) design space exploration, (3) system level verification, (4) hardware/software co-simulation, and (5) whole-system performance analysis and optimization .
The Open Core Protocol"International Partnership (OCP-IP)  Consortium has defined a high-performance and bus-independent interface protocol between IPs, usually referred to as the OCP Protocol, which provides a standard for a system designer such that the design time of the core interface can be greatly reduced and possible interface errors can be discovered at the early design stage. OCP defines a point-to-point socket interface specification that enables comprehensive and standardized definitions of a semiconductor IP core's on-chip interface. The IP cores can be a simple peripheral core, a high-performance microprocessor, or an on-chip communication system. Rather than defining rigid signal protocols that a core must implement, the OCP protocol provides a consistent framework for the identification of all kinds of on-chip data, test and control signals for IP cores.
Using OCP, IP designers can make their cores independent of some specific bus protocols, and hence the IP cores will be suitable for any particular design implementation. This makes it easier to reuse OCP-compliant cores across multiple SOC designs. Traditionally designers have to support different bus protocols by modifying a core's interface, the verification suite, the test bench, the documentation, and all other interface-related design issues of the core. OCP eliminates the need to repeatedly modify the core itself, and preserves the verification and test benches by defining all the core's natural interface capabilities in an unchanging, universally understood manner. As a result, significantly improved IP core reusability can be achieved, which leads directly to more predictable and productive SoC designs.
In the next two sections we shall describe the various abstraction levels for data communication (called layers) and the signals defined in OCP interface, respectively. In addition, as the channel models of OCP protocol are still under development, some changes on the protocol or the channel models are expected in the future releases. For the users of the OCP-IP SLD kit that has been provided by the OCP-IP System Level Design (SLD) Working Group to help design OCP-compatible interface, one critical feature of the kit is its stability, i.e., the properties that have been verified in previous release must be maintained in later releases. In order to do so, a regression test method has to be developed to help ensure the functionality that the many users of the OCP-IP SLD kit have come to rely upon is maintained release after release. We have developed a suite of test cases for this purpose, which will be detailed in Section 4.
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