December 07, 2007 -- edadesignline.com
Over the past decade, designers around the world have argued over the relative merits of using ASICs or FPGAs to implement digital electronic designs. This ongoing discussion has typically positioned the performance advantages and low power consumption of fully customized ICs against the flexibility and low NRE costs of FPGAs. Should a design team make the formidable up-front NRE investment in an ASIC design in order to maximize performance, reduce footprint and drive down costs at high volumes? Or is the design team building an end product for a market that demands the highly configurable feature sets and quick turnaround that only FPGAs can provide?
Surprisingly, the escalating challenges of high-density IC design are, in many ways, making that argument irrelevant. As ASIC designers migrate to each new process node, designs grow more complex, software content increases and verification runtimes lengthen. Moreover, recent research indicates that over 60 percent of respun ASICs fail not because of issues with timing or power, but because of logical or functional errors. For this reason, functional verification has become the single most critical phase of the ASIC development cycle, and often the most time-consuming. An increasing number of ASIC designers find that they can best meet their requirements by prototyping the functional equivalents of their designs as FPGAs. In fact, more than 90 percent of all ASICs today are either partially or completely prototyped as FPGAs before tape-out. Thus the question is no longer whether to implement an IC design as an ASIC, or as an FPGA. To meet the demands of today's markets, most design teams must do both.
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